Components irradiation test no. 15 - 2N708, 2N918, S2N1486 and S2N2412 transistors and 2N2498 field effect transistor
Neutron and gamma radiation effects on field effect transistor and injection transistors
RADIATION EFFECT↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Complementary transistor-transistor logic /CTTL/ - An approach to high-speed micropower logic.
Description of a new approach to micropower integrated circuits that is called complementary transistor-transistor logic (CTTL). This logic combines the inherent low standby power of a complementary inverter with the high speed of the TTL-type input. Results of monolithic fabricated circuits are presented. These circuits are shown to be equally adaptable to hybrid and discrete circuitry.
Stehlin, R. A.↗
Metal Oxide Semiconductor /MOS/ transistor research and development program. Part II - Development of stable complementary MOS FIELD effect transistors Final report, Mar. - Nov. 1965
Simultaneous fabrication of enhancement mode metal oxide semiconductor transistors in epitaxial material
TRANSISTOR↗
Impact of 12-nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level
Here, this article presents a comparative analysis of total ionizing dose (TID) response in GlobalFoundries’ (GF) 12 low-power (LP) and 12LP+12-nm bulk fin field effect transistor (FinFET) technologies using 10-keV X-rays. Our findings show that 12LP+ n-type transistors demonstrate higher sensitivity to TID degradation of the off-state leakage drain current compared to 12LP. Data indicate that for both 12LP and 12LP+, transistors with higher threshold voltages (VTs) exhibit lower off-state drain-source leakage postirradiation compared to transistors with lower VTs. Data consistently show that transistors with fewer fins per transistor show superior TID tolerance, in both 12LP and 12LP+ technologies. Lower VT transistors in both technologies display similar preirradiation leakage currents. On the other hand, higher VT transistors in 12LP+ show lower preirradiation leakage currents than those in 12LP, highlighting that the front-end-of-line of 12LP+ technology has been modified compared to 12LP. p-type devices in 12LP+ presented negligible degradation. Larger TID sensitivity in 12LP+ might be attributed to the implementation of dual-metal gate work functions, reduced halo doping, deeper source/drain (S/D) doping profiles, and/or 12LP+ having narrower fins compared to 12LP.
Dual-metal gate work functions↗
Efficient and Robust p-Type Transistor Based on Ultrawide-Bandgap Semiconductor
The p-type transistor is an indispensable component of semiconductor technology, enabling a complementary operation with n-channel transistors for computation, storage, and communication. Achieving both high robustness and high efficiency is highly desirable but challenging for p-type transistors due to the limited semiconductors with reliable hole transport and their high activation energies. Here, in this study, we achieved a robust yet efficient p-type transistor by heterogeneously integrating an ultrawide-bandgap semiconductor and a high-κ dielectric layer through van der Waals integration. The p-type transistor employs a two-dimensional hole channel on hydrogenated diamond (bandgap 5.6 eV) combined with a high-κ (30.5) SrTiO 3 perovskite membrane. At room temperature, the transistor exhibits stable operation with a high on-current (∼200 mA/mm), low subthreshold swing (70 mV/dec), high hole mobility (566 cm 2 /(V·s) to 572 cm 2 /(V·s)), and high on–off ratio (∼10 9 ). Furthermore, tuning the annealing temperature allows operation in either enhancement or depletion mode. The robust p-type transistor with high efficiency holds great potential for future power electronics, ultraviolet (UV) optoelectronics, and harsh-environment electronic applications.
high-κ membrane↗
Gyrator employing field effect transistors
A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.
Hochmair, E. S.↗
Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective
The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.
gate-all-around transistors↗
Mobility and threshold voltage extraction in transistors with gate-voltage-dependent contact resistance
The mobility of emerging (e.g., two-dimensional, oxide, organic) semiconductors is commonly estimated from transistor current-voltage measurements. However, such devices often experience contact gating, i.e., electric fields from the gate modulate the contact resistance during measurements, which can lead conventional extraction techniques to estimate mobility incorrectly even by a factor >2. Although this error can be minimized by measuring transistors at high gate-source bias |V gs |, this regime is often inaccessible in emerging devices that suffer from high contact resistance or early gate dielectric breakdown. Here, we propose a method of extracting mobility in transistors with gate-dependent contact resistance that does not require operation at high |V gs |, enabling accurate mobility extraction even in emerging transistors with strong contact gating. Our approach relies on updating the transfer length method (TLM) and can achieve <10% error even in regimes where conventional techniques overestimate mobility by >2×
36 MATERIALS SCIENCE↗
Investigating the Effects of Individual Neutron-Induced Defects in Bipolar Junction Transistors
Here, this study investigates neutron-induced displacement damage in Bipolar Junction Transistors (BJTs) using TCAD models informed by Deep-Level-Transient-Spectroscopy (DLTS) data. These models are calibrated and validated against experimental measurements performed at various neutron fluences. Both npn and pnp transistor configurations are studied to analyze the effects of individual traps on carrier recombination and base leakage currents. In npn transistors, deep traps (0.42 eV from the conduction band) dominate at low voltages, while shallow traps (0.17 eV from the conduction band) become prominent at higher voltages. Conversely, pnp transistors have base leakage current predominantly due to deep-level traps. The study observes a notable trend in trap density versus fluence, characterized by a linear relationship on a log-log scale. These insights into defect evolution under radiation conditions are crucial for optimizing semiconductor device reliability and performance in radiation-prone environments.
42 ENGINEERING↗
2 kV Al 0.64 Ga 0.36 N-channel high electron mobility transistors with passivation and field plates
Abstract High voltage (∼2 kV) Al 0.64 Ga 0.36 N-channel high electron mobility transistors were fabricated with an on-resistance of ∼75 Ω. mm (∼21 mΩ. cm 2 ). Two field plates of variable dimensions were utilized to optimize the breakdown voltage. The breakdown voltage reached >3 kV (tool limit) before passivation however it reduced to ∼2 kV after Si 3 N 4 surface passivation and field plate deposition. The breakdown voltage and on-resistance demonstrated a strong linear correlation in a scattered plot of ∼50 measured transistors. The fabricated transistors were electrically characterized and benchmarked against the state-of-the-art high-voltage (> 1 kV) Al-rich (>40%) AlGaN-channel transistors in breakdown voltage and on-resistance, indicating significant progress.
Alam, Md Tahmidul (ORCID:000900086556839X)↗
Ultra-stable oscillator with complementary transistors
A high frequency oscillator, having both good short and long term stability, is formed by including a piezoelectric crystal in the base circuit of a first bi-polar transistor circuit, the bi-polar transistor itself operated below its transitional frequency and having its emitter load chosen so that the input impedance, looking into the base thereof, exhibits a negative resistance in parallel with a capacitive reactance. Combined with this basic circuit is an auxiliary, complementary, second bi-polar transistor circuit of the same form with the piezoelectric crystal being common to both circuits. By this configuration small changes in quiescent current are substantially cancelled by opposite variations in the second bi-polar transistor circuit, thereby achieving from the oscillator a signal having its frequency of oscillation stable over long time periods as well as short time periods.
Kleinberg, L. L.↗
Development and fabrication of improved power transistor switches
A new class of high-voltage power transistors has been achieved by adapting present interdigitated thyristor processing techniques to the fabrication of NPN Si transistors. Present devices are 2.3 cm in diameter. The electrical performance obtained is consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The forward safe operating area of the experimental transistors shows a significant improvement over commercially available devices. The report describes device design, wafer processing, and various measurements which include dc characteristics, forward and reverse second breakdown limits, and switching times.
Hower, P. L.↗
Development and fabrication of improved power transistor switches
A new class of high-voltage power transistors was achieved by adapting present interdigitated thyristor processing techniques to the fabrication of npn Si transistors. Present devices are 2.3 cm in diameter and have V sub CEO (sus) in the range of 400 to 600V. V sub CEO (sus) = 450V devices were made with an (h sub FE)(I sub C) product of 900A at V sub CE = 2.5V. The electrical performance obtained was consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The device design, wafer processing, and assembly techniques are described. Experimental measurements of the dc characteristics, forward SOA, and switching times are included. A new method of characterizing the switching performance of power transistors is proposed.
Hower, P. L.↗
Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress
In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.
Mclyman, W. T.↗
A PWM transistor inverter for an ac electric vehicle drive
A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.
Slicker, J. M.↗
A 10-kW series resonant converter design, transistor characterization, and base-drive optimization
The development, components, and performance of a transistor-based 10 kW series resonant converter for use in resonant circuits in space applications is described. The transistors serve to switch on the converter current, which has a half-sinusoid waveform when the transistor is in saturation. The goal of the program was to handle an input-output voltage range of 230-270 Vdc, an output voltage range of 200-500 Vdc, and a current limit range of 0-20 A. Testing procedures for the D60T and D7ST transistors are outlined and base drive waveforms are presented. The total device dissipation was minimized and found to be independent of the regenerative feedback ratio at lower current levels. Dissipation was set at within 10% and rise times were found to be acceptable. The finished unit displayed a 91% efficiency at full power levels of 500 V and 20 A and 93.7% at 500 V and 10 A.
Robson, R. R.↗
Emulation of Synaptic Plasticity in WO 3 ‐Based Ion‐Gated Transistors
Neuromorphic systems, inspired by the human brain, promise significant advancements in computational efficiency and power consumption by integrating processing and memory functions, thereby addressing the von Neumann bottleneck. This paper explores the synaptic plasticity of a WO3-based ion-gated transistor (IGT) in [EMIM][TFSI] and a 0.1 mol L −1 LiTFSI in [EMIM][TFSI] for neuromorphic computing applications. Cyclic voltammetry (CV), transistor characteristics, and atomic force microscopy (AFM) force–distance (FD) profiling analyses reveal that Li + brings about ion intercalation, together with higher mobility and conductance, and slower response time (τ). WO 3 IGTs exhibit spike amplitude-dependent plasticity (SADP), spike number-dependent plasticity (SNDP), spike duration-dependent plasticity (SDDP), frequency-dependent plasticity (FDP), and paired-pulse facilitation (PPF), which are all crucial for mimicking biological synaptic functions and understanding how to achieve different types of plasticity in the same IGT. The findings underscore the importance of selecting the appropriate ionic medium to optimize the performance of synaptic transistors, enabling the development of neuromorphic systems capable of adaptive learning and real-time processing, which are essential for applications in artificial intelligence (AI).
36 MATERIALS SCIENCE↗
Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors
It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.
BEOL↗