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Guaranteeing synchronous message deadlines with the timed token medium access control protocol

We study the problem of guaranteeing synchronous message deadlines in token ring networks where the timed token medium access control protocol is employed. Synchronous capacity, defined as the maximum time for which a node can transmit its synchronous messages every time it receives the token, is a key parameter in the control of synchronous message transmission. To ensure the transmission of synchronous messages before their deadlines, synchronous capacities must be properly allocated to individual nodes. We address the issue of appropriate allocation of the synchronous capacities. Several synchronous capacity allocation schemes are analyzed in terms of their ability to satisfy deadline constraints of synchronous messages. We show that an inappropriate allocation of the synchronous capacities could cause message deadlines to be missed even if the synchronous traffic is extremely low. We propose a scheme called the normalized proportional allocation scheme which can guarantee the synchronous message deadlines for synchronous traffic of up to 33 percent of available utilization. To date, no other synchronous capacity allocation scheme has been reported to achieve such substantial performance. Another major contribution of this paper is an extension to the previous work on the bounded token rotation time. We prove that the time elapsed between any consecutive visits to a particular node is bounded by upsilon TTRT, where TTRT is the target token rotation time set up at system initialization time. The previous result by Johnson and Sevcik is a special case where upsilon = 2. We use this result in the analysis of various synchronous allocation schemes. It can also be applied in other similar studies.

Agrawal, Gopal

Robust Timing Synchronization in Aeronautical Mobile Communication Systems

This work details a study of robust synchronization schemes suitable for satellite to mobile aeronautical applications. A new scheme, the Modified Sliding Window Synchronizer (MSWS), is devised and compared with existing schemes, including the traditional Early-Late Gate Synchronizer (ELGS), the Gardner Zero-Crossing Detector (GZCD), and the Sliding Window Synchronizer (SWS). Performance of the synchronization schemes is evaluated by a set of metrics that indicate performance in digital communications systems. The metrics are convergence time, mean square phase error (or root mean-square phase error), lowest SNR for locking, initial frequency offset performance, midstream frequency offset performance, and system complexity. The performance of the synchronizers is evaluated by means of Matlab simulation models. A simulation platform is devised to model the satellite to mobile aeronautical channel, consisting of a Quadrature Phase Shift Keying modulator, an additive white Gaussian noise channel, and a demodulator front end. Simulation results show that the MSWS provides the most robust performance at the cost of system complexity. The GZCD provides a good tradeoff between robustness and system complexity for communication systems that require high symbol rates or low overall system costs. The ELGS has a high system complexity despite its average performance. Overall, the SWS, originally designed for multi-carrier systems, performs very poorly in single-carrier communications systems. Table 5.1 in Section 5 provides a ranking of each of the synchronization schemes in terms of the metrics set forth in Section 4.1. Details of comparison are given in Section 5. Based on the results presented in Table 5, it is safe to say that the most robust synchronization scheme examined in this work is the high-sample-rate Modified Sliding Window Synchronizer. A close second is its low-sample-rate cousin. The tradeoff between complexity and lowest mean-square phase error determines the rankings of the Gardner Zero-Crossing Detector and both versions of the Early-Late Gate Synchronizer. The least robust models are the high and low-sample-rate Sliding Window Synchronizers. Consequently, the recommended replacement synchronizer for NASA's Advanced Air Transportation Technologies mobile aeronautical communications system is the high-sample-rate Modified Sliding Window Synchronizer. By incorporating this synchronizer into their system, NASA can be assured that their system will be operational in extremely adverse conditions. The quick convergence time of the MSWS should allow the use of high-level protocols. However, if NASA feels that reduced system complexity is the most important aspect of their replacement synchronizer, the Gardner Zero-Crossing Detector would be the best choice.

Xiong, Fu-Qin

Noncoherent DTTLs for Symbol Synchronization

Noncoherent data-transition tracking loops (DTTLs) have been proposed for use as symbol synchronizers in digital communication receivers. [Communication- receiver subsystems that can perform their assigned functions in the absence of synchronization with the phases of their carrier signals ( carrier synchronization ) are denoted by the term noncoherent, while receiver subsystems that cannot function without carrier synchronization are said to be coherent. ] The proposal applies, more specifically, to receivers of binary phase-shift-keying (BPSK) signals generated by directly phase-modulating binary non-return-to-zero (NRZ) data streams onto carrier signals having known frequencies but unknown phases. The proposed noncoherent DTTLs would be modified versions of traditional DTTLs, which are coherent. The symbol-synchronization problem is essentially the problem of recovering symbol timing from a received signal. In the traditional, coherent approach to symbol synchronization, it is necessary to establish carrier synchronization in order to recover symbol timing. A traditional DTTL effects an iterative process in which it first generates an estimate of the carrier phase in the absence of symbol-synchronization information, then uses the carrier-phase estimate to obtain an estimate of the symbol-synchronization information, then feeds the symbol-synchronization estimate back to the carrier-phase-estimation subprocess. In a noncoherent symbol-synchronization process, there is no need for carrier synchronization and, hence, no need for iteration between carrier-synchronization and symbol- synchronization subprocesses. The proposed noncoherent symbolsynchronization process is justified theoretically by a mathematical derivation that starts from a maximum a posteriori (MAP) method of estimation of symbol timing utilized in traditional, coherent DTTLs. In that MAP method, one chooses the value of a variable of interest (in this case, the offset in the estimated symbol timing) that causes a likelihood function of symbol estimates over some number of symbol periods to assume a maximum value. In terms that are necessarily oversimplified to fit within the space available for this article, it can be said that the mathematical derivation involves a modified interpretation of the likelihood function that lends itself to noncoherent DTTLs. The proposal encompasses both linear and nonlinear noncoherent DTTLs. The performances of both have been computationally simulated; for comparison, the performances of linear and nonlinear coherent DTTLs have also been computationally simulated. The results of these simulations show that, among other things, the expected mean-square timing errors of coherent and noncoherent DTTLs are relatively insensitive to window width. The results also show that at high signal-to-noise ratios (SNRs), the performances of the noncoherent DTTLs approach those of their coherent counterparts at, while at low SNRs, the noncoherent DTTLs incur penalties of the order of 1.5 to 2 dB.

Simon, Marvin

Time Synchronization and Distribution Mechanisms for Space Networks

This work discusses research on the problems of synchronizing and distributing time information between spacecraft based on the Network Time Protocol (NTP), where NTP is a standard time synchronization protocol widely used in the terrestrial network. The Proximity-1 Space Link Interleaved Time Synchronization (PITS) Protocol was designed and developed for synchronizing spacecraft that are in proximity where proximity is less than 100,000 km distant. A particular application is synchronization between a Mars orbiter and rover. Lunar scenarios as well as outer-planet deep space mother-ship-probe missions may also apply. Spacecraft with more accurate time information functions as a time-server, and the other spacecraft functions as a time-client. PITS can be easily integrated and adaptable to the CCSDS Proximity-1 Space Link Protocol with minor modifications. In particular, PITS can take advantage of the timestamping strategy that underlying link layer functionality provides for accurate time offset calculation. The PITS algorithm achieves time synchronization with eight consecutive space network time packet exchanges between two spacecraft. PITS can detect and avoid possible errors from receiving duplicate and out-of-order packets by comparing with the current state variables and timestamps. Further, PITS is able to detect error events and autonomously recover from unexpected events that can possibly occur during the time synchronization and distribution process. This capability achieves an additional level of protocol protection on top of CRC or Error Correction Codes. PITS is a lightweight and efficient protocol, eliminating the needs for explicit frame sequence number and long buffer storage. The PITS protocol is capable of providing time synchronization and distribution services for a more general domain where multiple entities need to achieve time synchronization using a single point-to-point link.

Woo, Simon S.

Verification of fault-tolerant clock synchronization systems

A critical function in a fault-tolerant computer architecture is the synchronization of the redundant computing elements. The synchronization algorithm must include safeguards to ensure that failed components do not corrupt the behavior of good clocks. Reasoning about fault-tolerant clock synchronization is difficult because of the possibility of subtle interactions involving failed components. Therefore, mechanical proof systems are used to ensure that the verification of the synchronization system is correct. In 1987, Schneider presented a general proof of correctness for several fault-tolerant clock synchronization algorithms. Subsequently, Shankar verified Schneider's proof by using the mechanical proof system EHDM. This proof ensures that any system satisfying its underlying assumptions will provide Byzantine fault-tolerant clock synchronization. The utility of Shankar's mechanization of Schneider's theory for the verification of clock synchronization systems is explored. Some limitations of Shankar's mechanically verified theory were encountered. With minor modifications to the theory, a mechanically checked proof is provided that removes these limitations. The revised theory also allows for proven recovery from transient faults. Use of the revised theory is illustrated with the verification of an abstract design of a clock synchronization system.

Miner, Paul S.

Toward Time Synchronization in Delay Tolerant Network based Solar System Internetworking

The expanding presence in space will place an increased dependency on networked communications– a scalable communications infrastructure; that is, the Solar System Internet (SSI). Upcoming developments towards a SSI include NASA’s upcoming LunaNet, or lunar Internet, which provides multi-hop multi-path communications using Delay Tolerant Networking (DTN). DTN has been an active area of research and development, particularly in routing, security, and optimization. DTNs are marked by mobility, disconnection, and a wide variance of latencies (propagation and processing delays). In this paper, we outline progress towards a theory of time synchronization across such a network. An underlying assumption of DTN is that the network is time synchronized already, rather than synchronization being provided as a service. While this is necessary for schedule-based routing, which is necessarily prevalent in DTNs, it is so deeply ingrained as to be built into the primary unit of data in DTNs– the bundle. Indeed, a bundle’s creation timestamp and its time to live (called the lifetime) are based on time, and there are special recommendations for systems that lack accurate clocks. The assumption of time synchronization makes sense when limiting considerations to smaller-scale and more traditional space communication. However, just as end-to-end connectivity cannot be guaranteed in DTNs, neither can access to a reference or authoritative clock. In this more general case, it might be necessary to synchronize over time-varying meshes, and perhaps even to consider relativistic effects. Moreover, by imposing synchronization restrictions in order to sustain a network, the effectiveness of the network to achieve scalability will be necessarily muted. To work towards a time synchronization theory for DTNs, we build upon past successes in modeling DTNs using time-varying graphs and sheaves. This includes error and limitation estimation, which allows one to define domains over which schedule-based routing is possible, up to some threshold sensitivity. Despite the theoretical nature of these results, the approaches taken are also algorithmic, and hence lend themselves to practical implementations. The paper concludes with comparisons of the various methods along with suggestions for future work.

Delay Tolerant Networking

Fault-tolerant clock synchronization in distributed systems

Existing fault-tolerant clock synchronization algorithms are compared and contrasted. These include the following: software synchronization algorithms, such as convergence-averaging, convergence-nonaveraging, and consistency algorithms, as well as probabilistic synchronization; hardware synchronization algorithms; and hybrid synchronization. The worst-case clock skews guaranteed by representative algorithms are compared, along with other important aspects such as time, message, and cost overhead imposed by the algorithms. More recent developments such as hardware-assisted software synchronization and algorithms for synchronizing large, partially connected distributed systems are especially emphasized.

Ramanathan, Parameswaran

Global synchronization algorithms for the Intel iPSC/860

In a distributed memory multicomputer that has no global clock, global processor synchronization can only be achieved through software. Global synchronization algorithms are used in tridiagonal systems solvers, CFD codes, sequence comparison algorithms, and sorting algorithms. They are also useful for event simulation, debugging, and for solving mutual exclusion problems. For the Intel iPSC/860 in particular, global synchronization can be used to ensure the most effective use of the communication network for operations such as the shift, where each processor in a one-dimensional array or ring concurrently sends a message to its right (or left) neighbor. Three global synchronization algorithms are considered for the iPSC/860: the gysnc() primitive provided by Intel, the PICL primitive sync0(), and a new recursive doubling synchronization (RDS) algorithm. The performance of these algorithms is compared to the performance predicted by communication models of both the long and forced message protocols. Measurements of the cost of shift operations preceded by global synchronization show that the RDS algorithm always synchronizes the nodes more precisely and costs only slightly more than the other two algorithms.

Seidel, Steven R.

The two-way time synchronization system via a satellite voice channel

A newly developed two-way time synchronization system is described in this paper. The system uses one voice channel at a SCPC satellite digital communication earth station, whose bandwidth is only 45 kHz, thus saving satellite resources greatly. The system is composed of one master station and one or several, up to sixty-two, secondary stations. The master and secondary stations are equipped with the same equipment, including a set of timing equipment, a synthetic data terminal for time synchronizing, and a interface unit between the data terminal and the satellite earth station. The synthetic data terminal for time synchronization also has an IRIG-B code generator and a translator. The data terminal of master station is the key part of whole system. The system synchronization process is full automatic, which is controlled by the master station. Employing an autoscanning technique and conversational mode, the system accomplishes the following tasks: linking up liaison with each secondary station in turn, establishing a coarse time synchronization, calibrating date (years, months, days) and time of day (hours, minutes, seconds), precisely measuring the time difference between local station and the opposite station, exchanging measurement data, statistically processing the data, rejecting error terms, printing the data, calculating the clock difference and correcting the phase, thus realizing real-time synchronization from one point to multiple points. We also designed an adaptive phase circuit to eliminate the phase ambiguity of the PSK demodulator. The experiments have shown that the time synchronization accuracy is better than 2 mu S. The system has been put into regular operation.

Heng-Qiu, Zheng

System Synchronizes Recordings from Separated Video Cameras

A system of electronic hardware and software for synchronizing recordings from multiple, physically separated video cameras is being developed, primarily for use in multiple-look-angle video production. The system, the time code used in the system, and the underlying method of synchronization upon which the design of the system is based are denoted generally by the term "Geo-TimeCode(TradeMark)." The system is embodied mostly in compact, lightweight, portable units (see figure) denoted video time-code units (VTUs) - one VTU for each video camera. The system is scalable in that any number of camera recordings can be synchronized. The estimated retail price per unit would be about $350 (in 2006 dollars). The need for this or another synchronization system external to video cameras arises because most video cameras do not include internal means for maintaining synchronization with other video cameras. Unlike prior video-camera-synchronization systems, this system does not depend on continuous cable or radio links between cameras (however, it does depend on occasional cable links lasting a few seconds). Also, whereas the time codes used in prior video-camera-synchronization systems typically repeat after 24 hours, the time code used in this system does not repeat for slightly more than 136 years; hence, this system is much better suited for long-term deployment of multiple cameras.

Nail, William

Synchronous rotation in magnetic X-ray binaries

AM Herculis is thought to be a binary stellar system that contains an accreting magnetic degenerate dwarf whose rotation is synchronous with the orbital period. This synchronism is remarkable, particularly because of the small moment of inertia of a degenerate dwarf and the large specific angular momentum of the accreted matter. This paper demonstrates that ohmic dissipation from the magnetic interaction of the stars is capable of bringing about exact synchronism, provided that some other process has brought the rotation period of the degenerate dwarf to the same order of magnitude as the orbital period. It is also shown that magnetostatic interaction in the synchronous state leads to oscillatory drifts in phase about exact synchronism with periods of approximately 1-10 yr. These phase drifts could manifest themselves in long-term periodic variability in the X-ray or optical properties of the source. Accretion torques could excite such oscillatory motions but need not disrupt synchronism once it has been established.

Joss, P. C.

Synchronization Scheme For PPM Communication

Synchronization achieved under difficult, low-signal conditions. Synchronization scheme for pulse-position modulation (PPM) matches pulse, word, and frame timeslots of receiver to received signals to ensure proper identification of received pulses. Involves brief sequence of synchronizing pulses within each transmitted frame and relies on periodic repetition of synchronizing pulses for verification. Use of verification reduces number of synchronizing pulses required but increases time required to achieve synchronization.

Marshall, William K.

SPEEDES - A multiple-synchronization environment for parallel discrete-event simulation

Synchronous Parallel Environment for Emulation and Discrete-Event Simulation (SPEEDES) is a unified parallel simulation environment. It supports multiple-synchronization protocols without requiring users to recompile their code. When a SPEEDES simulation runs on one node, all the extra parallel overhead is removed automatically at run time. When the same executable runs in parallel, the user preselects the synchronization algorithm from a list of options. SPEEDES currently runs on UNIX networks and on the California Institute of Technology/Jet Propulsion Laboratory Mark III Hypercube. SPEEDES also supports interactive simulations. Featured in the SPEEDES environment is a new parallel synchronization approach called Breathing Time Buckets. This algorithm uses some of the conservative techniques found in Time Bucket synchronization, along with the optimism that characterizes the Time Warp approach. A mathematical model derived from first principles predicts the performance of Breathing Time Buckets. Along with the Breathing Time Buckets algorithm, this paper discusses the rules for processing events in SPEEDES, describes the implementation of various other synchronization protocols supported by SPEEDES, describes some new ones for the future, discusses interactive simulations, and then gives some performance results.

Steinman, Jeff S.

Reliable interface design for combining asynchronous and synchronous circuits

In order to successfully integrate asynchronous and synchronous designs, great care must be taken at the interface between the two types of systems. Synchronizing asynchronous inputs with a free running clock can cause well-known problems with metastability in the synchronization circuits. Stretchable clocks allow a clock cycle to expand dynamically in response to the metastability effects of sampling asynchronous inputs. We use an interface organization where the special circuitry for detecting metastability and for stretching the clock that is delivered to the synchronous part of the system is encapsulated in a Q-flop-based interface. This provides a very convenient method for interfacing mixed systems, as the interface and clock generation circuitry are isolated into one special module, and neither the asynchronous nor the synchronous system need be modified internally to accommodate the interface. This is especially important when standard synchronous components are used as there is no opportunity to modify these parts. We show that this interface module is suitable for most mixed design needs and conclude with an example.

Josephson, Lueli

Modulation and synchronization technique for MF-TDMA system

This report addresses modulation and synchronization techniques for a multi-frequency time division multiple access (MF-TDMA) system with onboard baseband processing. The types of synchronization techniques analyzed are asynchronous (conventional) TDMA, preambleless asynchronous TDMA, bit synchronous timing with a preamble, and preambleless bit synchronous timing. Among these alternatives, preambleless bit synchronous timing simplifies onboard multicarrier demultiplexer/demodulator designs (about 2:1 reduction in mass and power), requires smaller onboard buffers (10:1 to approximately 3:1 reduction in size), and provides better frame efficiency as well as lower onboard processing delay. Analysis and computer simulation illustrate that this technique can support a bit rate of up to 10 Mbit/s (or higher) with proper selection of design parameters. High bit rate transmission may require Doppler compensation and multiple phase error measurements. The recommended modulation technique for bit synchronous timing is coherent QPSK with differential encoding for the uplink and coherent QPSK for the downlink.

Faris, Faris

Phase Synchronization and Desynchronization of Structural Response Induced by Turbulent and External Sound

Acoustic and turbulent boundary layer flow loadings over a flexible structure are used to study the spatial-temporal dynamics of the response of the structure. The stability of the spatial synchronization and desynchronization by an active external force is investigated with an array of coupled transducers on the structure. In the synchronous state, the structural phase is locked, which leads to the formation of spatial patterns while the amplitude peaks exhibit chaotic behaviors. Large amplitude, spatially symmetric loading is superimposed on broadband, but in the desynchronized state, the spectrum broadens and the phase space is lost. The resulting pattern bears a striking resemblance to phase turbulence. The transition is achieved by using a low power external actuator to trigger broadband behaviors from the knowledge of the external acoustic load inducing synchronization. The changes are made favorably and efficiently to alter the frequency distribution of power, not the total power level. Before synchronization effects are seen, the panel response to the turbulent boundary layer loading is discontinuously spatio-temporally correlated. The stability develops from different competing wavelengths; the spatial scale is significantly shorter than when forced with the superimposed external sound. When the external sound level decreases and the synchronized phases are lost, changes in the character of the spectra can be linked to the occurrence of spatial phase transition. These changes can develop broadband response. Synchronized responses of fuselage structure panels have been observed in subsonic and supersonic aircraft; results from two flights tests are discussed.

Maestrello, Lucio

A Methodology for the Design and Verification of Globally Asynchronous/Locally Synchronous Architectures

Recent advanced in model-checking have made it practical to formally verify the correctness of many complex synchronous systems (i.e., systems driven by a single clock). However, many computer systems are implemented by asynchronously composing several synchronous components, where each component has its own clock and these clocks are not synchronized. Formal verification of such Globally Asynchronous/Locally Synchronous (GA/LS) architectures is a much more difficult task. In this report, we describe a methodology for developing and reasoning about such systems. This approach allows a developer to start from an ideal system specification and refine it along two axes. Along one axis, the system can be refined one component at a time towards an implementation. Along the other axis, the behavior of the system can be relaxed to produce a more cost effective but still acceptable solution. We illustrate this process by applying it to the synchronization logic of a Dual Fight Guidance System, evolving the system from an ideal case in which the components do not fail and communicate synchronously to one in which the components can fail and communicate asynchronously. For each step, we show how the system requirements have to change if the system is to be implemented and prove that each implementation meets the revised system requirements through modelchecking.

Miller, Steven P.

Frame Synchronization Without Attached Sync Markers

We describe a method to synchronize codeword frames without making use of attached synchronization markers (ASMs). Instead, the synchronizer identifies the code structure present in the received symbols, by operating the decoder for a handful of iterations at each possible symbol offset and forming an appropriate metric. This method is computationally more complex and doesn't perform as well as frame synchronizers that utilize an ASM; nevertheless, the new synchronizer acquires frame synchronization in about two seconds when using a 600 kbps software decoder, and would take about 15 milliseconds on prototype hardware. It also eliminates the need for the ASMs, which is an attractive feature for short uplink codes whose coding gain would be diminished by the overheard of ASM bits. The lack of ASMs also would simplify clock distribution for the AR4JA low-density parity-check (LDPC) codes and adds a small amount to the coding gain as well (up to 0.2 dB).

Hamkins, Jon