Analysis of PTL routes for LSI of superconducting logic circuits.
Abstract not provided.
Lewis, Rupert M.↗
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Advancements in NbTiN based circuits for Superconducting Digital Logic
Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.
Pokhrel, A. [Imec,Heverlee,Belgium]↗
Two Circuits for Directing and Controlling Ballistic Fluxons
Reversible logic schemes using flux solitons (fluxons) on long Josephson junctions (LJJs) have recently been proposed. The attraction of the fluxon is that it propagates ballistically along an LJJ until it encounters a change in the character of the LJJ, often a designed circuit element. Logic gates involve fluxons interacting with circuit elements and with other fluxons. However, testing of ballistic fluxon circuits requires other circuits outside the logic family to direct and control fluxon motion. Here we discuss two such non-reversible fluxon control circuits. First, the polarity filter gate is a simple non-reversible gate that allows one polarity of fluxon to pass, while reflecting the other polarity. In the off state both polarities reflect. Second, the polarity separator generalizes on the polarity filter concept and allows separation of the two fluxon polarities into different LJJs. We discuss simulations of these structures and possible applications.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Integrating magnetic Co-nanopillars in a NbN-based VAN thin film as a multifunctional hybrid metamaterial
NbN thin films are considered as a promising alternative candidate to conventional Al superconducting electrodes for Josephson junction devices, superconducting qubits and quantum logic circuits. Herein, by co-growing ferromagnetic Co with superconducting NbN, self-assembled NbN–Co vertically aligned nanocomposite (VAN) thin films have been successfully deposited on a MgO substrates, with NbN in its cubic superconducting phase. The obtained VAN metamaterials exhibit epitaxial growth of NbN with uniformly dispersed Co nanoplates. Further physical property characterization reveals that the NbN–Co VAN presents ferromagnet properties with strong out-of-plane magnetic anisotropy and optical anisotropy. This hybrid metamaterial system could find future applications in superconducting spintronic devices and quantum computing devices.
Zhang, Yizhi [Purdue Univ., West Lafayette, IN (Un↗
A nanocryotron memory and logic family
The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 - 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Analog-to-digital converter based on voltage-controlled superconducting devices
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.
Analog-to-digital converter↗
Unconventional compute methods and future challenges for superconducting digital computing
Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.
EDA tools↗
Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications
Here this paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6 μW and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.
42 ENGINEERING↗
Prototype Parts of a Digital Beam-Forming Wide-Band Receiver
Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.
Kaplan, Steven B.↗
Superconducting Hyperdimensional Associative Memory Circuit for Scalable Machine Learning
Here we propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of ~ 2-20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78-84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Magnetic flux imaging in a 3D superconductor integrated circuit
We report on imaging magnetic flux distributions in a multilayered superconductor integrated circuit which emerge during magnetization and after field cooling of the circuit in the DC magnetic field. The obtained complicated field maps expose the flux propagation across the patterned superconducting ground planes sandwiching layers with Josephson junction-based logic cells, fine wire grid around the functional units, and multiple superconducting fill structures located in different inner layers. The observed intricate flux distributions are explained by specific patterns of Meissner screening currents and superconducting critical currents in different mutually interacting parts of the integrated circuit. Our results provide important insights into possible ways of improving the protection of superconductor integrated circuits from magnetic fields and their resilience against flux trapping.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Strong parametric dispersive shifts in a statically decoupled two-qubit cavity QED system
Qubits in cavity quantum electrodynamic (QED) architectures are often operated in the dispersive regime, in which the operating frequency of the cavity depends on the energy state of the qubit, and vice versa. The ability to tune these dispersive shifts provides additional options for performing either quantum measurements or logical manipulations. Here we couple two transmon qubits to a lumped-element cavity through a shared superconducting quantum interference device (SQUID). In this work, our design balances the mutual capacitive and inductive circuit components so that both qubits are statically decoupled from the cavity with low flux sensitivity, offering protection from decoherence processes. Parametric driving of the SQUID flux enables independent, dynamical tuning of each qubit’s interaction with the cavity. As a practical demonstration, we perform pulsed parametric dispersive readout of both qubits. The dispersive frequency shifts of the cavity mode follow the theoretically expected magnitude and sign. This parametric approach creates an extensible, tunable cavity QED framework with various future applications, such as entanglement and error correction via multi-qubit parity readout, state and entanglement stabilization, and parametric logical gates.
77 NANOSCIENCE AND NANOTECHNOLOGY↗
Flex-PCB Quench Antenna Developments at FNAL
We report flexible printed-circuit-board-based quench antenna arrays have been developed at FNAL since 2017. They proved to be low-noise, low-cost, sensitive, and non-invasive sensors for quench characterization in superconducting magnets, having the potential to extend even to quench detection. Starting with applications of small area sensors of this type, we have explored feasibility for operations at high pressure, and have invested in multi-channel quench antenna arrays covering the complete area of the innermost magnet layer of the conductor. We've also tested and optimized sensor geometry and relative orientations to increase sensitivity and spatial resolution. Beyond developments of warm and cold bore antennas, we've progressed to concepts which attach quench antennas to the conductor surfaces of accelerator magnets. Multiple programs and projects at FNAL and collaborating institutions benefited from this work already and our plans target further extensions of capabilities and applicability of these devices. In this paper we present the logic behind the development steps taken so far, status of our work and direction of near-term research on quench antennas at Fermilab.
43 PARTICLE ACCELERATORS↗
High-T c Superconducting Memory Cell
In this paper, operational principles of a cryogenic memory cell that utilizes high-temperature superconductors (high-T c ) are presented. Such a cell consists of three inductively coupled Josephson junctions coupled via inductors. Design and operational logic of this type of cell were recently introduced and demonstrated for low temperature 4 K environment. The basic memory cell operations (read, write, reset) can be implemented on the same simple circuit and both destructive and non-destructive memory cell operations can be realized. Here, we present the design principles and computational validation of basic memory cell operations (write, read, and reset) for the high-T c memory cell. In conclusion, our results for the high-T c memory cell operations show very good resemblance with the previously presented low-temperature 4 K memory cell operations.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Autonomous quantum error correction and fault-tolerant quantum computation with squeezed cat qubits
We propose an autonomous quantum error correction scheme using squeezed cat (SC) code against excitation loss in continuous-variable systems. Through reservoir engineering, we show that a structured dissipation can stabilize a two-component SC while autonomously correcting the errors. The implementation of such dissipation only requires low-order nonlinear couplings among three bosonic modes or between a bosonic mode and a qutrit. While our proposed scheme is device independent, it is readily implementable with current experimental platforms such as superconducting circuits and trapped-ion systems. Compared to the stabilized cat, the stabilized SC has a much lower dominant error rate and a significantly enhanced noise bias. Furthermore, the bias-preserving operations for the SC have much lower error rates. In combination, the stabilized SC leads to substantially better logical performance when concatenating with an outer discrete-variable code. The surface-SC scheme achieves more than one order of magnitude increase in the threshold ratio between the loss rate κ 1 and the engineered dissipation rate κ 2 . Under a practical noise ratio κ 1 /κ 2 = 10 -3 , the repetition-SC scheme can reach a 10 -15 logical error rate even with a small mean excitation number of 4, which already suffices for practically useful quantum algorithms.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Real-time quantum error correction beyond break-even
The ambition of harnessing the quantum for computation is at odds with the fundamental phenomenon of decoherence. The purpose of quantum error correction (QEC) is to counteract the natural tendency of a complex system to decohere. This cooperative process, which requires participation of multiple quantum and classical components, creates a special type of dissipation that removes the entropy caused by the errors faster than the rate at which these errors corrupt the stored quantum information. Previous experimental attempts to engineer such a process faced an excessive generation of errors that overwhelmed the error-correcting capability of the process itself. Whether it is practically possible to utilize QEC for extending quantum coherence thus remains an open question. We answer it by demonstrating a fully stabilized and error-corrected logical qubit whose quantum coherence is significantly longer than that of all the imperfect quantum components involved in the QEC process, beating the best of them with a coherence gain of G=2.27±0.07. Here we achieve this performance by combining innovations in several domains including the fabrication of superconducting quantum circuits and model-free reinforcement learning.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Characterizing and Modeling the Influence of Geometry on the Performance of Superconducting Nanowire Cryotrons
The scaling of superconducting nanowire detectors to larger arrays is often limited by room-temperature-readout cabling. Cryogenic integrated circuits constructed from nanowire cryotrons, or nanocryotrons, can address this limitation by performing signal processing on chip. In this study, we characterize key performance metrics of the nanocryotron to elucidate its potential as a logical element in cryogenic integrated circuits and develop an electro-thermal model to connect material parameters with device performance. We find that the performance of the nanocryotron depends on the device geometry, and trade-offs are associated with optimizing the gain, jitter, and energy dissipation. Here, we demonstrate that nanocryotrons fabricated on niobium nitride can achieve a grey zone less than 210 nA wide for a 5 ns long input pulse corresponding to a maximum achievable gain of 48 dB, an energy dissipation of less than 20 aJ per operation, and a jitter of less than 60 ps.
Superconductor↗