Fragmentation Analysis of High-Energy Heavy Ion Beams for Single-Event Effects Testing at NSRL
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Report presents test data on susceptibility of new set of digital integrated circuits and other semiconductor products to single-event effects (soft errors and latchups) caused by heavy ions incident at high energies. Data used to develop generalizations for protecting electronic equipment from single-event effects. In some cases, tested parts selected as candidates for use in specific applications.
Various papers on nuclear and space radiation effects are presented. The general topics addressed include: basic mechanisms of radiation effects, dosimetry and energy-dependent effects, hardness assurance and testing techniques, single-event upset and latchup, isolation technologies, device and integrated circuit effects and hardening, spacecraft charging and electromagnetic effects.
Various papers on nuclear science are presented. The general topics addressed are: basic mechanisms of radiation effects, dosimetry and energy-dependent effects, isolation technologies, device radiation response and hardening, microcircuit radiation response and hardening, single-event phenomena, hardness assurance and testing techniques, spacecraft charging, space environments and effects.
The effects of nuclear and space radiation on the performance of electronic devices are discussed in reviews and reports of recent investigations. Topics addressed include the basic mechanisms of radiation effects, dosimetry and energy-dependent effects, sensors in and for radiation environments, EMP/SGEMP/IEMP phenomena, radiation effects on isolation technologies, and spacecraft charging and space radiation effects. Consideration is given to device radiation effects and hardening, hardness assurance and testing techniques, IC radiation effects and hardening, and single-event phenomena.
We present data on the vulnerability of a variety of candidate spacecraft electronics to proton and heavy-ion induced single-event effects and proton-induced damage. Devices tested include optoelectronics, digital, analog, linear bipolar, hybrid devices, Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs), and DC-DC converters, among others.
Report describes experimental study of use of microelectronic advanced laser scanner (MEALS) to cause single-event upsets (SEUs) in integrated logic circuits. Basic concepts of SEU testing by use of MEALS described in "Laser Scanner Tests for Single-Event Upsets" (NPO-18216), "Single-Event-Upset Laser Scanner With Optical Bias" (NPO-18217), and "More About Laser Scanner Tests for Single-Event Upsets" (NPO-18494). Study part of continuing effort to study SEU effects of ionizing radiation on such circuits and to use MEALS as relatively inexpensive SEU-prescreening laboratory apparatus serving as alternative to heavy-ion acclerator.
A picosec pulsed dye laser beam was at selected wavelengths successfully used to simulate heavy-ion single-event effects (SEEs) in negative channel NMOS DRAMs. A DRAM was used to develop the test technique because bit-mapping capability and previous heavy-ion upset data were available. The present analysis is the first to establish such a correlation between laser and heavy-ion data for devices, such as the NMOS DRAM, where charge collection is dominated by long-range diffusion, which is controlled by carrier density at remote distances from a depletion region. In the latter case, penetration depth is an important parameter and is included in the present analysis. A single-pulse picosecond dye laser beam (1.5 microns diameter) focused onto a single cell component can upset a single memory cell; clusters of memory cell upsets (multiple errors) were observed when the laser energy was increased above the threshold energy. The multiple errors were analyzed as a function of the bias voltage and total energy of a single pulse. A diffusion model to distinguish the multiple upsets from the laser-induced charge agreed well with previously reported heavy ion data.
Data taken from tests involving heavy ions in the Berkeley 88 in. cyclotron being directed at low power Schottky barrier devices are reported. The tests also included trials in the Harvard cyclotron with 130 MeV protons, and at the U.C. Davis cyclotron using 56 MeV protons. The experiments were performed to study the single event upsets in MSI logic devices containing flip-flops. Results are presented of single-event upsets (SEU) causing functional degradation observed in post-exposure tests of six different devices. The effectiveness of the particles in producing SEUs in logic device functioning was found to be directly proportional to the proton energy. Shielding was determined to offer negligible protection from the particle bombardment. The results are considered significant for the design and fabrication of LS devices for space applications.
Microelectronic advanced laser scanner (MEALS) is opto/electro/mechanical apparatus for nondestructive testing of integrated memory circuits, logic circuits, and other microelectronic devices. Multipurpose diagnostic system used to determine ultrafast time response, leakage, latchup, and electrical overstress. Used to simulate some of effects of heavy ions accelerated to high energies to determine susceptibility of digital device to single-event upsets.
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Various papers on nuclear science are presented. The general topics addressed include: basic mechanics of radiation effects, dosimetry and energy-dependent effects, hardness assurance and testing techniques, spacecraft charging and space radiation effects, EMP/SGEMP/IEMP phenomena, device radiation effects and hardening, radiation effects on isolation technologies, IC radiation effects and hardening, and single-event phenomena.
We report on the SEE and TID tests of higher density flash memories. Stand-by currents and full functional tests were used to characterize the response of radiation effects.
This paper presents the results of reliability life testing performed on commercial electronic devices that experienced non-destructive single-event latch-up (SEL) during heavy-ion testing.
We present data on the vulnerability of a variety of candidate spacecraft electronics to proton and heavy-ion induced single-event effects and proton-induced damage. We also present data on the susceptibility of parts to functional degradation resulting from total ionizing dose at low dose rates (0.003-0.33 Rads(Si)/s). Devices tested include optoelectronics, digital, analog, linear bipolar, hybrid devices, Analog to Digital Converters (ADCs), Digital to Analog Converters (DACs), and DC-DC converters, among others.
Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.
Various papers on nuclear and space radiation effects are presented. The general topics addressed include: basic mechanisms of radiation effects, single-event phenomena, temperature and field effects, modeling and characterization of radiation effects, IC radiation effects and hardening, and EMP/SGEMP/IEMP phenomena. Also considered are: dosimetry/energy-dependent effects, sensors in and for radiation environments, spacecraft charging and space radiation effects, radiation effects and devices, radiation effects on isolation technologies, and hardness assurance and testing techniques.
Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.