Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Single Event Upsets”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2017

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

single event effect (SEE)↗
NASA NTRS1990

Anomalies due to single event upsets

The description of single event upsets (SEUs) in the spacecraft Anomalies Handbook is reviewed. The basic mechanism involved in SEUs is summarized and discussed in terms of circuit analysis. Calculation of SEU rate is analytically described and discussed. Departures from single step function dependence in the SEU rate is addressed.

Robinson, P. A., Jr.↗
NASA NTRS2006

Frequency Dependence of Single-Event Upset in Highly Advanced PowerPC Microprocessors

Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes at three frequencies of 500, 1066 and 1600 MHz. Frequency dependence of single-event upsets is discussed. The results of our studies suggest the single-event upset in registers and D-Cache tend to increase with frequency. This might have important implications for the overall single-event upset trend as technology moves toward higher frequencies.

Cyclotron↗
NASA NTRS2004

Frequency Dependence of Single-event Upset in Advanced Commerical PowerPC Microprocessors

This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency. Results are presented for SOI processors with feature sizes of 0.18 microns and two different core voltages. Single-event upset from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequency up to 1GHz. Frequency and core voltage dependence of single-event upsets in registers is discussed.

single-event upset (SEU)↗
NASA NTRS2003

Single-event upset in advanced commercial power PC microprocessors

Single-event upset from heavy ions in measured for advanced commercial microprocessors, comparing upset sensitivity in registers and d-cache for several generations of devices. Multiple-bit upsets and asymmetry in registers upset cross sections are also discussed.

single-event upset advanced commercial power PC pr↗
NASA NTRS1986

Testing Electronic Devices for Single-Event Upset

Report prepared describes equipment and summarizes both pretest and onsite procedures for testing of digital electronic devices for susceptibility to single-event upset. Term "single-event upset" denotes variety of temporary or permanent bit flips or latchup induced by single particles of ionizing radiation. Vacuum chamber houses device under test while exposed to ion beam. Vacuum chamber and associated equipment must be brought to ion-beam facility for test.

Nichols, D. K.↗
NASA NTRS1989

Effects of cosmic rays on single event upsets

Assistance was provided to the Brookhaven Single Event Upset (SEU) Test Facility. Computer codes were developed for fragmentation and secondary radiation affecting Very Large Scale Integration (VLSI) in space. A computer controlled CV (HP4192) test was developed for Terman analysis. Also developed were high speed parametric tests which are independent of operator judgment and a charge pumping technique for measurement of D(sub it) (E). The X-ray secondary effects, and parametric degradation as a function of dose rate were simulated. The SPICE simulation of static RAMs with various resistor filters was tested.

Venable, D. D.↗
NASA NTRS2004

Frequency dependence of single-event upset in advanced commercial PowerPC microprocessors

Single-event upset (SEU) from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequencies up to 1 GHz. Frequency and core voltage dependence of SEUs in registers and D-Cache are discussed. The results of our studies suggest the SEU in registers and D-Cache tend to increase with frequency. This might have important implications for the overall SEU trend as technology moves toward higher frequencies.

Farmanesh, F. F.↗
NASA NTRS2008

Characterizing SRAM Single Event Upset in Terms of Single and Double Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAM s state is shown to be based upon the resistive path from the p+-sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are then predicted and compared to recent SRAM test data.

Black, J. D.↗
NASA NTRS1997

Single-Event Upset in Flash Memories

This paper discusses single-event upset effets in flash memories, using heavy ions at the Texas A&M cyclotron. Initial results are presented for one manufacturer that compare uspet in the individual memory elemts with the more complex funtion failure modes that occur in the internal state machine and its control registers. This device is designed to function with either 5-V or 3.3-V power supply levels for read operations, but requires an additional 5 or 12-V power supply for write and erase operations.

Flash↗
NASA NTRS2016

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets in a NAND Flash Memory

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found that the single-event upset (SEU) cross section varied inversely with cumulative fluence. We attribute the effect to the variable upset sensitivities of the memory cells. Furthermore, the effect impacts only single cell upsets in general. The rate of multiple-bit upsets remained relatively constant with fluence. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, traditional SEE testing techniques may underestimate the on-orbit event rate for a device with variable upset sensitivity.

NAND flash memory↗
NASA NTRS2002

Single-event upset in advanced PowerPC microprocessors

Proton and heavy-ion single-event upset susceptibility has been measured for the MotorolaPowerPC7400. The results show that this advanced device has low upset susceptibility, despite the scaling and design advances.

radiation single-event upset↗
NASA NTRS2016

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets of NAND Flash Memory

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence. We attribute the effect to the variable upset sensitivities of the memory cells. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, heavy ion irradiation of devices with variable upset sensitivity distribution using typical fluence levels may underestimate the cross section and on-orbit event rate.

Single Event Effects (SEE)↗
NASA NTRS2004

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

single event upset (SEU)↗
NASA NTRS2010

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Ng, Tak-kwong↗
NASA NTRS2003

Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets (MBU) in registers and were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors was discussed.

Yoder, G. I.↗
NASA NTRS1984

A guideline for heavy ion radiation testing for Single Event Upset (SEU)

A guideline for heavy ion radiation testing for single event upset was prepared to assist new experimenters in preparing and directing tests. How to estimate parts vulnerability and select an irradiation facility is described. A broad brush description of JPL equipment is given, certain necessary pre-test procedures are outlined and the roles and testing guidelines for on-site test personnel are indicated. Detailed descriptions of equipment needed to interface with JPL test crew and equipment are not provided, nor does it meet the more generalized and broader requirements of a MIL-STD document. A detailed equipment description is available upon request, and a MIL-STD document is in the early stages of preparation.

Nichols, D. K.↗