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It is believed that the increase in SEUs with more modern devices may have serious consequences for future space missions. The physics behind an SEU is discussed as well as SEU test philosophy and equipment, and testing results. It is concluded that the problem may be ameliorated by careful device selection and the use of redundancy or error correction.
A guideline for heavy ion radiation testing for single event upset was prepared to assist new experimenters in preparing and directing tests. How to estimate parts vulnerability and select an irradiation facility is described. A broad brush description of JPL equipment is given, certain necessary pre-test procedures are outlined and the roles and testing guidelines for on-site test personnel are indicated. Detailed descriptions of equipment needed to interface with JPL test crew and equipment are not provided, nor does it meet the more generalized and broader requirements of a MIL-STD document. A detailed equipment description is available upon request, and a MIL-STD document is in the early stages of preparation.
Here, we present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm 2 /mg.
New test data have been combined with published data to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. These data have been arranged to exibit the SEU susceptibility of devices by function, technology, and manufacturer. Clear trends emerge which should be useful in predicting future device performance.
New test data from the Jet Propulsion Laboratory (JPL), The Aerospace Corporation, Rockwell International (ANAHEIM) and IRT have been combined with published data of JPL and Aerospace to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. This data has been arranged to exhibit the SEU susceptibility of devices by function, technology and manufacturer. Clear trends emerge which should be useful in predicting future device performance.
The authors collected a set of heavy-ion single event upset (SEU) test data since their last publication in December, 1985. Trends in SEU susceptibility for state-of-the-art parts are presented.
Assistance was provided to the Brookhaven Single Event Upset (SEU) Test Facility. Computer codes were developed for fragmentation and secondary radiation affecting Very Large Scale Integration (VLSI) in space. A computer controlled CV (HP4192) test was developed for Terman analysis. Also developed were high speed parametric tests which are independent of operator judgment and a charge pumping technique for measurement of D(sub it) (E). The X-ray secondary effects, and parametric degradation as a function of dose rate were simulated. The SPICE simulation of static RAMs with various resistor filters was tested.
The results of single-event upset (SEU) testing performed to evaluate the parametric transients, i.e., amplitude and duration, in several I/O devices, and the impact of these transients are discussed. The failure rate of these devices is dependent on the susceptibility of interconnected devices to the resulting transient change in the output of the I/O device. This failure rate, which is a function of the susceptibility of the interconnected device as well as the SEU response of the I/O device itself, may be significantly different from an upset rate calculated without taking these factors into account. The impact at the system level is discussed by way of an example.
Charge collection exhibited by p-n junctions, which have at least one small dimension, deviates from the geometric assumptions commonly used in SEU (single event upset) testing. The amount of charge collected did not increase with the secant of the angle of incidence. The number of events under the peak in the charge collection spectrum did not decrease as the cosine of the angle of incidence. Both the position of the peak and the number of events under the peak measured at a given angle of incidence depended upon which symmetry axis of the device was chosen to be the axis of rotation.
This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
This paper presents viewgraphs of Antifuse FPGA (Field Programmable Gate Array) for Space Applications. The topics include: 1) A32140DX TID Test; 2) A1280XL Proton Test; 3) SEU (Single Event Upsets) Rate Calculation; 4) Recent Products Test; 5) A1460A TID (Traveling Ionospheric Disturbances) Test; 6) I100 Proton Test; 7) 100/RHI100 SEU Test; 8) I100/RH100 TID Test; 9) A1020S TID Test; 10) TID Charge Pump Failure; 11) Radiation Testing; and SEE (Single Event Effects) Test Setup.
This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
The data summarized describe single event upset (bit-flips) for 60 device types having data storage elements. The data are from 15 acceleration tests with both protons and heavier ions. Tables are included summarizing the upset threshold data and listing the devices tested for heavy ion induced bit-flip and the devices tested with protons. With regard to the proton data, it is noted that the data are often limited to one proton energy, since the tests were usually motivated by the engineering requirement of comparing similar candidate devices for a system. It is noted that many of the devices exhibited no upset for the given test conditions (the maximum fluence and the maximum proton energy Ep are given for these cases). It is believed, however, that some possibility of upset usually exists because there is a slight chance that the recoil atom may receive up to 10 to 20 MeV of recoil energy (with more energy at higher Ep).
We propose a method for the application of single event upset (SEU) data towards the analysis of complex systems using transformed reliability models (from the time domain to the particle fluence domain) and space environment data.
We present SEU test and analysis of the Microsemi ProASIC3 FPGA. SEU Probability models are incorporated for device evaluation. Included is a comparison to the RTAXS FPGA illustrating the effectiveness of the overall testing methodology.
Single event upset (SEU) and latchup vulnerabilities were determined for a number of parts of interest to NASA space programs. In cases where a threshold linear energy transfer (LET) for SEU could be measured, an upset rate in a low inclination Space Shuttle orbit was computed. The predicted upset rates are extremely low, except for the devices with LET thresholds below the geomagnetic cutoff for altitude and inclination of the Space Shuttle orbit. While some of the devices do exhibit latchup, the cross sections and threshold LETs are such that the risk associated with flying these devices in low, near equatorial orbits is small if not negligible.
Finite state-machines (FSMs) are used to control operational flow in application specific integrated circuits (ASICs) and field programmable gate array (FPGA) devices. Because of their ease of interpretation, FSMs simplify the design and verification process and consequently are significant components in a synchronous design.