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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Pulsed Infrared Thermography Nondestructive Imaging of SiC-SiC f Composite Cladding Architectures; Understanding the Performance of SiC-SiC f Composite Cladding Architectures with Cr Coating in Normal Operating and Accident Conditions in LWRs and Advanced Reactors

SiC-SiC f composites, consisting of silicon carbide fibers embedded in a silicon carbide matrix, are advanced materials with high thermal conductivity, temperature stability, and resistance to radiation damage. Traditional methods for quality control of fabricated SiC-SiC f composites involve nondestructive evaluation (NDE) with X-ray computed tomography (XCT). However, XCT imaging of typical SiC-SiC f structures for cladding applications can involve several hours. In this project, we investigate an alternative approach to NDE of SiC-SiC f composites that involves rapid (on the order of seconds) imaging with Pulsed infrared thermography (PIT). PIT images of a planar SiC-SiC f specimen show the structure of the surface monolith layer and internal SiC f structures. The capability of PIT imaging in visualizing SiC f structures is qualitatively confirmed by observing similarity in the PIT and X-ray transmission images of the same specimen. Computer vision analysis of defects in the PIT image of the monolith was performed with thresholding followed by topological structural analysis that computed geometric descriptors, including major/minor axes of fitted ellipses, area, perimeter, Feret diameter, circularity, roundness, and solidity.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
NASA NTRS1991

Controlled growth of 3C-SiC and 6H-SiC films on low-tilt-angle vicinal (0001) 6H-SiC wafers

It has been found that, with proper pregrowth surface treatment, 6H-SiC single-crystal films can be grown by chemical vapor deposition (CVD) at 1450 C on vicinal (0001) 6H-SiC with tilt angles as small as 0.1 deg. Previously, tilt angles of greater than 1.5 deg were required to achieve 6H on 6H at this growth temperature. In addition, 3C-SiC could be induced to grow within selected regions on the 6H substrate. the 3C regions contained few (or zero) double-positioning boundaries and a low density of stacking faults. A new growth model is proposed to explain the control of SiC polytype in this epitaxial film growth process.

Powell, J. A.↗
NASA NTRS1992

Growth and characterizaton of 3C-SiC and 6H-SiC films on 6H-SiC wafers

Single crystal SiC films were grown by CVD on vicinal (0001) SiC wafers cut from boules produced by the modified sublimation method. Wafers with tilt angles less than 0.5 deg yielded 3C-SiC; tilt angles of 3 to 4 deg resulted in 6H-SiC films. The surface morphology of these films, up to 24 microns thick, were investigated as a function of growth parameters such as the Si/C ratio in the input gases and the presence of dopant materials such as nitrogen and trimethylaluminum.

Powell, J. A.↗
DOE OSTI2025

Thermal mechanical assessment of a SiC-SiC-composite clad fuel pin concept in a light water reactor environment

Accident Tolerant Fuels (ATFs) are designed to increase coping time following an accident scenario while preserving or improving current steady state reactor operational performance. A potential ATF concept is SiC-SiC composite claddings. Fuel performance simulations were conducted on a SiC-SiC based cladding concept utilizing a multilayered approach for improved performance. This cladding concept referred to as the Duplex concept is a duplex structure composed of a monolithic SiC layer placed on the outside of a SiC-SiC composite. A liquid metal is added to fuel-cladding gap for improved heat dissipation from the fuel. The monolithic SiC layer is used to improve the coolant corrosion characteristics and protect the SiC-SiC composite layer from exposure to the coolant. The fuel performance code BISON was used to conduct fuel performance simulations on the cladding concepts. Comparisons are made with a current prototypic fuel rod design (UO 2 fuel enclosed in Zircaloy-4 cladding). Representative steady-state cases were considered for normal power and two cycle power histories. Additionally, a PCI ramp case was simulated to analyze potential anticipated operational occurrences. Transient response during a Loss of Coolant Accident and a Reactivity Initiated Accident were also simulated. This computational study demonstrated that for normal operating conditions, the SiC concept cladding performed as well as the baseline for the standard power cases evaluated. The ramping evaluations indicate potential fracturing of the SiC-SiC composite of the composite cladding compared to the Zircaloy-4 cladding due to the temperature gradient and the subsequent differential thermal conductivity degradation and swelling across the composite thickness. In conclusion, the rod fails early at low enthalpy for RIA but survives a LOCA with minimal material loss due to high temperature steam corrosion.

11 - NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗
DOE OSTI2025

Design, Fabrication and On-Sun Performance Evaluation of SiC Receiver Feature Specimens for CST Applications Using Additively Manufactured SiC Materials

Increasing operating temperatures of solar receivers is paramount to the efficiency of concentrated solar thermal (CST) and solar power (CSP) systems. Successful development of CST systems to generate heat for industrial applications requires significant increase in temperature capability and techno-economically viability of the receiver systems. Supported by an award from the Solar Technology Office (SETO), US Department of Energy (DOE), GE Aerospace Research in collaboration with Heliogen Holdings Inc and Sandia National Lab, is engaged in the development of ultra-High Operating Temperature SiC-matrix Solar Thermal Air Receiver (HOTSSTAR) enabled by additive manufacturing. The program objective is to demonstrate SiC receiver with air exit temperatures up to 1100 oC and high thermal efficiencies. We report design, fabrication and on-sun test results of SiC components of a prototype 50kW (thermal) HOTSSTAR module. The receiver module architecture is based on a radial airflow design and consists of a series of radial SiC receiver sectors organized around a SiC center absorber. The SiC components are fabricated using binder-jet printed SiC followed by melt-infiltration reaction bonding process. To enhance the reliability and to minimize the risk of cracking damage of SiC test articles in thermal gradient and thermal shock environment of the application, the components were laminated with GE’s MI SiC-SiC CMC. Following extensive design and lab test analyses, selected SiC component designs are tested at Heliogen Lancaster Solar field under highly concentrated solar fluxes around 2000 suns to assess the thermal performance characteristics under realistic field conditions. We report on the test results and compare the thermal performances of different HOTSSTAR SiC absorbers. Finally, we discuss fabrication and initial assembly of a 50kW prototype test module in preparation of on-sun field tests to assess the performance of our final design.

CST, CSP, high temperature, air receiver, SiC, add↗
NASA NTRS1994

Electrical properties of epitaxial 3C- and 6H-SiC p-n junction diodes produced side-by-side on 6H-SiC substrates

3C-SiC (beta-SiC) and 6H-SiC p-n junction diodes have been fabricated in regions of both 3C-SiC and 6H-SiC epitaxial layers which were grown side-by-side on low-tilt-angle 6H-SiC substrates via a chemical vapor deposition (CVD) process. Several runs of diodes exhibiting state-of-the-art electrical characteristics were produced, and performance characteristics were measured and compared as a function of doping, temperature, and polytype. The first 3C-SiC diodes which rectify to reverse voltages in excess of 300 V were characterized, representing a six-fold blocking voltage improvement over experimental 3C-SiC diodes produced by previous techniques. When placed under sufficient forward bias, the 3C-SiC diodes emit significantly bright green-yellow light while the 6H-SiC diodes emit in the blue-violet. The 6H-SiC p-n junction diodes represent the first reported high-quality 6H-SiC devices to be grown by CVD on very low-tilt-angle (less than 0.5 deg off the (0001) silicon face) 6H substrates. The reverse leakage current of a 200 micron diameter circular device at 1100 V reverse bias was less than 20 nA at room temperature, and excellent rectification characteristics were demonstrated at the peak characterization temperature of 400 C.

EPITAXIAL LAYER↗
NASA NTRS2007

Growth and Characterization of 3C-SiC and 2H-AIN/GaN Films and Devices Produced on Step-Free 4H-SiC Mesa Substrates

While previously published experimental results have shown that the step-free (0 0 0 1) 4H-SiC mesa growth surface uniquely enables radical improvement of 3C-SiC and 2H-AlN/GaN heteroepitaxial film quality (greater than 100-fold reduction in extended defect densities), important aspects of the step-free mesa heterofilm growth processes and resulting electronic device benefits remain to be more fully elucidated. This paper reviews and updates recent ongoing studies of 3C-SiC and 2H-AlN/GaN heteroepilayers grown on top of 4H-SiC mesas. For both 3C-SiC and AlN/GaN films nucleated on 4H-SiC mesas rendered completely free of atomic-scale surface steps, TEM studies reveal that relaxation of heterofilm strain arising from in-plane film/substrate lattice constant mismatch occurs in a remarkably benign manner that avoids formation of threading dislocations in the heteroepilayer. In particular, relaxation appears to occur via nucleation and inward lateral glide of near-interfacial dislocation half-loops from the mesa sidewalls. Preliminary studies of homojunction diodes implemented in 3C-SiC and AlN/GaN heterolayers demonstrate improved electrical performance compared with much more defective heterofilms grown on neighbouring stepped 4H-SiC mesas. Recombination-enhanced dislocation motion known to degrade forward-biased 4H-SiC bipolar diodes has been completely absent from our initial studies of 3C-SiC diodes, including diodes implemented on defective 3C-SiC heterolayers grown on stepped 4H-SiC mesas.

Neudeck, P. G.↗
DOE OSTI2025

Improved damage tolerance of SiC-based nuclear fuel cladding with novel multi-layered SiC coating design at 1200 °C

Continuous SiC fibre reinforced SiC matrix composites (SiC f -SiC m ) with monolithic SiC outer coatings are considered as a damage-tolerant cladding design for loss of coolant accident (LOCA) conditions in light water reactors. However, monolithic SiC coatings are brittle and prone to catastrophic failure. In this study, a SiC f -SiC m cladding with a novel multi-layer SiC outer coating (11 sub-layers, ∼260 µm in total thickness) was investigated under C-ring compression at room temperature and 1200 °C in argon environment. Real-time synchrotron X-ray computed tomography (XCT) was employed to capture crack initiation and propagation processes. Compared to conventional monolithic SiC outer coatings, the multi-layer coating structure facilitated crack deflection and bifurcation enhancing its damage tolerance at both temperatures. Despite pre-existing surface cracks, claddings exhibited stable mechanical-performance at both temperatures. These initial cracks did not critically affect the failure processes as they were not aligned with the maximum stress direction. Furthermore, the microstructure, distribution of residual stresses, and local properties of individual components in the material were thoroughly characterized, and compared with open literature on conventional claddings with monolithic outer coatings. These results provide new insights into the failure mechanisms of multi-layer SiC coatings and offer guidance for the future design of accident-tolerant nuclear fuel claddings.

36 - MATERIALS SCIENCE↗
NASA NTRS1998

Oxygen Impurities and Defects in Epitaxial Layer SiC and SiC Wafer Characterized by Room and Low Temperatures FTIR

SiC as a highly promising semiconducting material has received increasing attention in the last decade. The impurities such as oxygen and hydrogen have a great effect in electronic properties of semiconducting materials. In this study, the FTIR spectra were measured at room temperature (25 C) and low temperature (-70 C) for an n-type SiC substrate, a p-type epitaxial layer SiC, and patterned Ta on a p-type epitaxial layer SiC sample. The oxygen related IR peaks were measured for all three samples at room and low temperatures. The peak at 1105 cm(exp -1) is the result of a substitutional carbon and a interstitial oxygen in SiC. The concentration of the impurity oxygen increases in the SiC epitaxial layer during the CVD and electron beam processes. For the n-type SiC substrate, this peak does not appear. The peak at 905 cm(exp -1) exists in the IR spectra only for two epitaxial layer on p-type SiC substrate samples. This peak is related to oxygen vacancy centers in SiC, which are introduced in the CVD epitaxial growth process. At low temperature, the peak at 1105 cm(exp -1) shifts down and the peak at 905 cm(exp -1) shifts up for the epitaxial layer SiC samples. It can be explained that, at low temperatures, the stress increases due to the distorted bonds. The study shows that FTIR is a very effective method to evaluate low concentration impurities in SiC.

Lu, W. J.↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
NASA NTRS2002

Growth of Defect-Free 3C-Sic on 4H- and 6H-SIC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3C-SiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (Delta/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS2004

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

Speer, Kevin M.↗
NASA NTRS1990

Growth of high quality 6H-SiC epitaxial films on vicinal (0001) 6H-SiC wafers

Previously reported growth of SiC films on SiC by chemical vapor deposition (CVD) used alpha-SiC crystal substrates. The CVD growth and evaluation of high quality 6H-SiC films on 6H-SiC wafers cut from large boules grown by the modified-sublimation process is reported. The single-crystal 6H-SiC films were grown on wafers oriented 3 to 4 deg off the (0001) plane toward the 11-20 direction. The films, up to 12 microns thick, had surfaces that were smooth and featureless. The high quality of the films was demonstrated by optical and electron microscopy, and low-temperature photoluminescence.

Powell, J. A.↗
NASA NTRS1996

Effect of Tilt Angle on the Morphology of SiC Epitaxial Films Grown on Vicinal (0001) SiC Substrates

In this study of 4H-SiC and 6H-SiC epitaxial films we found that film morphology was strongly dependent on the tilt angle of the substrate. Large surface steps (up to 25 nm high) due to step bunching were more prevalent at smaller tilt angles. Also, 4H films were more susceptible than 6H to 3C-SiC inclusions during growth. The lateral growth of steps from screw dislocations in low-tilt-angle substrates demonstrated that step bunching on the atomic scale was anisotropic with respect to growth direction for both 4H-SiC and 6H-SiC. A model explaining this behavior is presented. We observed and directly measured the Burgers vector of a 'super' screw dislocation in a 6H-SiC epilayer.

Powell, J. A.↗
NASA NTRS2004

Thermomechanical Performance of C and SiC Multilayer, Fiber-Reinforced, CVI SiC Matrix Composites

Hybrid fiber approaches have been attempted in the past to alloy desirable properties of different fiber-types for mechanical properties, thermal stress management, and oxidation resistance. Such an approach has potential for the CrSiC and SiCrSiC composite systems. SiC matrix composites with different stacking sequences of woven C fiber (T300) layers and woven Sic fiber (Hi-NicalonTM) layers were fabricated using the standard CVI process. Delamination occurred to some extent due to thermal mismatch for all of the composites. However, for the composites with a more uniform stacking sequence, minimal delamination occurred, enabling tensile properties to be determined at room temperature and elevated temperatures (stress-rupture in air). Composites were seal-coated with a CVI SiC layer as well as a proprietary C-B-Si (CBS) layer. Definite improvement in rupture behavior was observed in air for composites with increasing SiC fiber content and a CBS layer. The results will be compared to standard C fiber reinforced CVI SiC matrix and Hi-Nicalon reinforced CVI SiC matrix composites.

Morscher, Gregory N.↗
NASA NTRS2005

Measurements of Breakdown Field and Forward Current Stability in 3C-SiC P-N Junction Diodes Grown on Step-Free 4H-SiC

This paper reports on initial fabrication and electrical characterization of 3C-SiC p-n junction diodes grown on step-free 4H-SiC mesas. Diodes with n-blocking-layer doping ranging from approx. 2 x 10(exp 16)/cu cm to approx.. 5 x 10(exp 17)/cu cm were fabricated and tested. No optimization of junction edge termination or ohmic contacts was employed. Room temperature reverse characteristics of the best devices show excellent low-leakage behavior, below previous 3C-SiC devices produced by other growth techniques, until the onset of a sharp breakdown knee. The resulting estimated breakdown field of 3C-SiC is at least twice the breakdown field of silicon, but is only around half the breakdown field of <0001> 4H-SiC for the doping range studied. Initial high current stressing of 3C diodes at 100 A/sq cm for more than 20 hours resulted in less than 50 mV change in approx. 3 V forward voltage. 3C-SiC, pn junction, p+n diode, rectifier, reverse breakdown, breakdown field,heteroepitaxy, epitaxial growth, electroluminescence, mesa, bipolar diode

Neudeck, Philip G.↗
NASA NTRS2001

Growth of Defect-Free 3C-SiC on 4H- and 6H-SiC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3CSiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (delta a/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS1989

Nitriding kinetics of Si-SiC powder mixtures as simulations of reaction bonded Si3N4-SiC composites

The nitriding kinetics of Si and Si plus SiC powder mixtures were studied to simulate the fabrication of RBSN-SiC ceramic matrix composites. Very clean, assynthesized, and solvent-exposed powders were studied; C-rich and Si-rich SiC 0.04-0.05 micron diameter powders were mixed in varying concentrations with SiH4-derived 0.2-0.3 micron diameter Si powder. Complete nitridation is achieved with C-rich SiC powders in 140 min at 1250 C, and in the centers of Si-rich SiC powders in 15 min. The effects on the incubation periods, fast reaction periods, and slow reaction periods that characterize these nitriding processes were studied to explain unusual reverse reaction gradients and other effects of contamination.

Lightfoot, A.↗