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Results for “Separation circuit”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1999

Physically separating printed circuit boards with a resilient, conductive contact

A multi-board module provides high density electronic packaging in which multiple printed circuit boards are stacked. Electrical power, or signals, are conducted between the boards through a resilient contact. One end of the contact is located at a via in the lower circuit board and soldered to a pad near the via. The top surface of the contact rests against a via of the facing printed circuit board.

Baker, John D.↗
NASA NTRS1988

Variable-Speed, Constant-Frequency Generation Of Power

Feedback of stator power and reactive volt-amperes determines rotor excitation. New method involves control circuit separating rotor excitation into generation of slip frequency and control of amplitude and phase. In control circuit, speed determines slip frequency, while stator power and reactive volt-amperes determine amplitude and phase of rotor current.

Brady, Frank J.↗
DOE OSTI2021

Large gradients via correlation in random parameterized quantum circuits

Scaling of variational quantum algorithms to large problem sizes requires efficient optimization of random parameterized quantum circuits. For such circuits with uncorrelated parameters, the presence of exponentially vanishing gradients in cost function landscapes is an obstacle to optimization by gradient descent methods. In this work, we prove that reducing the dimensionality of the parameter space by utilizing circuit modules containing spatially or temporally correlated gate layers can allow one to circumvent the vanishing gradient phenomenon. Here, examples are drawn from random separable circuits and asymptotically optimal variational versions of Grover's algorithm based on the quantum alternating operator ansatz. In the latter scenario, our bounds on cost function variation imply a transition between vanishing gradients and efficient trainability as the number of layers is increased toward $\mathcal{O}\left({2}^{n/2}\right)$, the optimal oracle complexity of quantum unstructured search.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS1986

Redundant control system for X-wing valve actuators

The capability of compensating automatically for a failure in an actuator and the associated drive circuit is enhanced by providing a dual channel actuator, each channel having a drive coil and a position sensor tracking the position of the actuator output shaft. A separate circuit is provided for each actuator channel to detect drive loop failures and hydraulic failures. When the drive loop of one channel fails, it is disengaged, and the gain in the remaining drive loop is doubled to maintain authority. In an embodiment, the remaining drive loop cannot disengage when certain criteria, relating to the failure of associated actuators, are met. The invention is particularly useful for aerospace applications.

Arifian, Kenneth C.↗
NASA NTRS2009

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

DeGregorio, Kelly↗
DOE OSTI2021

Simplified feedback control system for scanning tunneling microscopy

A Scanning Tunneling Microscope (STM) is one of the most important scanning probe tools available to study and manipulate matter at the nanoscale. In a STM, a tip is scanned on top of a surface with a separation of a few Å. Often, the tunneling current between the tip and the sample is maintained constant by modifying the distance between the tip apex and the surface through a feedback mechanism acting on a piezoelectric transducer. This produces very detailed images of the electronic properties of the surface. The feedback mechanism is nearly always made using a digital processing circuit separate from the user computer. Here, we discuss another approach using a computer and data acquisition through the universal serial bus port. We find that it allows successful ultralow noise studies of surfaces at cryogenic temperatures. We show results on different compounds including a type II Weyl semimetal (WTe2), a quasi-two-dimensional dichalcogenide superconductor (2H–NbSe2), a magnetic Weyl semimetal (Co3Sn2S2), and an iron pnictide superconductor (FeSe).

Martín-Vega, Francisco (ORCID:0000000333177833)↗
NASA NTRS1979

Module failure isolation circuit for paralleled inverters

A module failure isolation circuit is described which senses and averages the collector current of each paralled inverter power transistor and compares the collector current of each power transistor the average collector current of all power transistors to determine when the sensed collector current of a power transistor in any one inverter falls below a predetermined ratio of the average collector current. The module associated with any transistor that fails to maintain a current level above the predetermined radio of the average collector current is then shut off. A separate circuit detects when there is no load, or a light load, to inhibit operation of the isolation circuit during no load or light load conditions.

Nagano, S.↗
NASA NTRS1969

Pulse-code-modulation baseline correction for low signal-to-noise ratios

Time-shared integrate-hold-dump circuits separate the dc level due to the signal /bit information/ from the dc signal due to the baseline error. The system detects the baseline error, filters it, and then algebraically adds enough voltage to a servo loop to reduce the error to zero.

Stephens, T. J.↗
NASA NTRS2001

Flight Computer Design for the Space Technology 5 (ST-5) Mission

As part of NASA's New Millennium Program, the Space Technology 5 mission will validate a variety of technologies for nano-satellite and constellation mission applications. Included are: a miniaturized and low power X-band transponder, a constellation communication and navigation transceiver, a cold gas micro-thruster, two different variable emittance (thermal) controllers, flex cables for solar array power collection, autonomous groundbased constellation management tools, and a new CMOS ultra low-power, radiation-tolerant, +0.5 volt logic technology. The ST-5 focus is on small and low-power. A single-processor, multi-function flight computer will implement direct digital and analog interfaces to all of the other spacecraft subsystems and components. There will not be a distributed data system that uses a standardized serial bus such as MIL-STD-1553 or MIL-STD-1773. The flight software running on the single processor will be responsible for all real-time processing associated with: guidance, navigation and control, command and data handling (C&DH) including uplink/downlink, power switching and battery charge management, science data analysis and storage, intra-constellation communications, and housekeeping data collection and logging. As a nanosatellite trail-blazer for future constellations of up to 100 separate space vehicles, ST-5 will demonstrate a compact (single board), low power (5.5 watts) solution to the data acquisition, control, communications, processing and storage requirements that have traditionally required an entire network of separate circuit boards and/or avionics boxes. In addition to the New Millennium technologies, other major spacecraft subsystems include the power system electronics, a lithium-ion battery, triple-junction solar cell arrays, a science-grade magnetometer, a miniature spinning sun sensor, and a propulsion system.

Speer, David↗
NASA NTRS2011

Management of the Post-Shuttle Extravehicular Mobility Unit (EMU) Water Circuits

The EMU incorporates two separate water circuits for the rejection of metabolic heat from the astronaut and the cooling of electrical components. The first (the Transport Water Loop) circulates in a semi-closed-loop manner and absorbs heat into a Liquid Coolant and Ventilation Garment (LCVG) warn by the astronaut. The second (the Feed Water Loop) provides water to a cooling device (Sublimator) with a porous plate, and that water subsequently sublimates to space vacuum. The cooling effect from the sublimation of this water translates to a cooling of the LCVG water that circulates through the Sublimator. Efforts are underway to streamline the use of a water processing kit (ALCLR) that is being used to periodically clean and disinfect the Transport Loop Water. Those efforts include a fine tuning of the duty cycle based on a review of prior performance data as well as an assessment of a fixed installation of this kit into the EMU backpack or within on-orbit EMU interface hardware. Furthermore, testing is being conducted to ensure compatibility between the International Space Station (ISS) Water Processor Assembly (WPA) effluent and the EMU Sublimator as a prelude to using the WPA effluent as influent to the EMU Feed Water loop. This work is undertaken to reduce the crew-time and logistics burdens for the EMU, while ensuring the long-term health of the EMU water circuits for a post-Shuttle 6-year service life.

Steele, John W.↗
NASA NTRS2012

Management of the Post-Shuttle Extravehicular Mobility Unit (EMU) Water Circuits

The EMU incorporates two separate water circuits for the rejection of metabolic heat from the astronaut and the cooling of electrical components. The first (the Transport Water Loop) circulates in a semi-closed-loop manner and absorbs heat into a Liquid Coolant and Ventilation Garment (LCVG) worn by the astronaut. The second (the Feed-water Loop) provides water to a cooling device (Sublimator) with a porous plate, and that water subsequently sublimates to space vacuum. The cooling effect from the sublimation of this water translates to a cooling of the LCVG water that circulates through the Sublimator. Efforts are underway to streamline the use of a water processing kit (ALCLR) that is being used to periodically clean and disinfect the Transport Loop Water. Those efforts include a fine tuning of the duty cycle based on a review of prior performance data as well as an assessment of a fixed installation of this kit into the EMU backpack, within on-orbit EMU interface hardware or as a stand-alone unit. Furthermore, testing is being conducted to ensure compatibility between the International Space Station (ISS) Water Processor Assembly (WPA) effluent and the EMU Sublimator as a prelude to using the WPA effluent as influent to the EMU Feed Water loop. This work is undertaken to reduce the crewtime and logistics burdens for the EMU, while ensuring the long-term health of the EMU water circuits for a 6-year service life.

Steele, John W.↗
NASA NTRS2016

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

JFET↗
NASA NTRS1976

Modular design of high frequency circuits

Method of circuit development separates electrical functions into noninterdependent parts, uses standard, commercially available circuit elements, and establishes unified circuit-packaging arrangement. Packaging scheme is cost-effective, does not compromise electrical circuit performance from video to UHF frequencies, and leaves circuits accessible for modification and adjustment.

Zimmer, J. T.↗
NASA NTRS2012

Wide Range SET Pulse Measurement

A method for measuring a wide range of SET pulses is demonstrated. Use of dynamic logic, faster than ordinary CMOS, allows capture of short pulses. A weighted binning of SET lengths allows measurement of a wide range of pulse lengths with compact circuitry. A pulse-length-conservative pulse combiner tree routes SETs from combinational logic to the measurement circuit, allowing SET measurements in circuits that cannot easily be arranged in long chains. The method is applied to add-multiplex combinational logic, and to an array of NFET routing switches, at .35 micron. Pulses are captured in a chain of Domino Logic AND gates. Propagation through the chain is frozen on the trailing edge by dropping low the second "enable" input to the AND gates. Capacitive loading is increased in the latter stages to create an approximately logarithmic weighted binning, so that a broad range of pulse lengths can be captured with a 10 stage capture chain. Simulations show pulses can be captured which are 1/5th the length of those typically captured with leading edge triggered latch methods, and less than the length of those captured with a trailing edge latch method. After capture, the pulse pattern is transferred to an SEU protected shift register for readout. 64 instances of each of two types of logic are used as targets. One is a full adder with a 4 to 1 mux on its inputs. The other is a 4 x 4 NFET routing matrix. The outputs are passed through buffered XNOR comparators to identify pulses, which are merged in a buffered not-nand (OR) tree designed to avoid pulse absorption as much as possible. The output from each of the two test circuits are input into separate pulse measurement circuits. Test inputs were provided so that the circuit could be bench tested and calibrated. A third SET measurement circuit with no inputs was used to judge the contribution from direct hits on the measurement circuit. Heavy ions were used with an LET range from 12 to 176. At LET of 21 and below, the very small number of SETs were not significantly higher in the test over the control circuits. At higher LET the test circuit SETs are one or two orders of magnitude greater than for the control circuit. The NFET circuit produces more and slightly longer SETs as expected. But the differences do not appear to be significant enough to modify strategies now used to avoid capture of SETs in chips such as FPGAs. Complete data and graphs will be in the full paper / presentation. In the summary figure below left, NOCL is the reference circuit without any input, and number of stages triggered is plotted. Simulation at right shows the smallest pulse captured (stage 2) at about 300 ps. Our conclusion is that the method is promising, but that improvements in the merge network are desirable before applying in a deep submicron process

Shuler, Robert L.↗