SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Simple, reliable, inexpensive method for gross-leak testing has been devised, based upon the conventional fine-leak technique. The sensitivity ranges from the detection of very large leaks down to leaks of 10 to the minus seven cc helium per sec.
Destructive and nondestructive testing, results, and specifications for reliability of integrated circuit and semiconductor devices
For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk.
The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.
A typical set up used to perform lifetime tests of packaged, fiber pigtailed semiconductor lasers is described, as well as tests performed on a set of four pump lasers. It was found that two lasers failed after 3200, and 6100 hours under device specified bias conditions at elevated temperatures. Failure analysis of the lasers indicates imperfections and carbon contamination of the laser metallization, possibly from improperly cleaned photo resist. SEM imaging of the front facet of one of the lasers, although of poor quality due to the optical fiber charging effects, shows evidence of catastrophic damage at the facet. More stringent manufacturing controls with 100% visual inspection of laser chips are needed to prevent imperfect lasers from proceeding to packaging and ending up in space applications, where failure can result in the loss of a space flight mission.
Components for a high-reliability system such as the Telstar project are obtained by: (a) design of the component for the required environment, (b) careful control of manufacturing processes, (c) elimination of potential early failures by screening tests, and (d) selection of the most stable components. For passive components, these methods could be applied by using design parameters, suppliers and screening techniques established in the earlier submarine cable program, with consideration being given to the additional effects of the satellite launch and orbit environments. Semiconductor component designs were selected by qualification tests using accelerated electrical and environmental stress conditions. Screening tests were applied to eliminate early failures, and resulting components were aged from two to six months before selection for the satellite. The recognition of the effect of ionizing radiation on transistors caused the addition of a radiation qualification test, or a screening to assure selection of the least sensitive devices. Tests have shown this screening to be effective for the radiation intensity expected. Experience with the passive components, and evaluation of the accelerated test results and aging data of the semiconductor devices, indicate that the reliability objective was obtained.
Techniques explored in search for rapid, reliable test. Resistances of aluminum/silicon contacts and methods to measure subjects of NASA report. Study with three tasks undertaken to evaluate nature and reliability of large numbers of semiconductor contacts of type now being fabricated in integrated circuits: Develop yield analysis for series strings of contacts using wafer-level electrical measurements, and identify different types of faults by visual inspection; develop wafer-level tests to evaluate reliability of contact strings; and develop mathematical model for current flow in contacts and examine contact region for evidence of micro-alloying.
The diode JANTX1N645-1 manufactured by Semtech and Micro Semiconductor was subjected to power/temperature step stress in order to assess its reliability. All test samples were subjected to electrical tests after completing the power/temperature step stress point. Control sample units were maintained for verification of the electrical parametric testing. Results are presented in tabular form.
The power systems for use in NASA space missions must work reliably under harsh conditions including radiation, thermal cycling, and exposure to extreme temperatures. Gallium nitride semiconductors show great promise, but information pertaining to their performance is scarce. Gallium nitride N-channel enhancement-mode field effect transistors made by EPC Corporation in a 2nd generation of manufacturing were exposed to radiation followed by long-term thermal cycling and testing under high temperature reverse bias conditions in order to address their reliability for use in space missions. Result of the experimental work are presented and discussed.
Fast scan infrared microscope for measuring thermal and electromechanical parameters affecting reliability of microelectronic devices
The failure of wire bonds due to repeated flexure when semiconductor devices are operated in an on-off mode has been investigated. An accelerated fatigue testing apparatus was constructed and the major fatigue variables, aluminum alloy composition, and bonding mechanism, were tested. The data showed Al-1% Mg wires to exhibit superior fatigue characteristics compared to Al-1% Cu or Al-1% Si and ultrasonic bonding to be better than thermocompression bonding for fatigue resistance. Based on these results highly reliable devices were fabricated using Al-1% Mg wire with ultrasonic bonding which withstood 120,000 power cycles with no failures.
Opto-coupler and light emitting diode (LED) failure mechanisms and associated activation energies were determind from the results of environmental and accelerated lift tests of over 2,400 devices. The evaluation program included LED phototransistor opto-couplers from three sources, LED photoamplifier opto-couplers from a single source, and discrete infrared emitting LEDs from two sources. Environmental tests to evaluate device mechanical integrity included power cycling (10,000 cycles), temperature cycling (500 cycles) and a sequence of monitored shock, monitored vibration and constant acceleration. Multiple temperature operating life tests were conducted at ambient temperatures between 25 C and 200 C. Opto-couplers were operated in both the 'on' and 'off' states during life testing.
Reliability analysis of the transistor JANTX2N4150 manufactured by General Semiconductor and Transitron is reported. The discrete devices were subjected to power and temperature step stress tests and then to electrical tests after completing the power/temperature step stress point. Control sample units were maintained for verification of the electrical parametric testing. Results are presented.
Fast scanning IR microscope for semiconductor evaluation used for engineering design analysis, reliability improvement, failure analysis, etc
In 1991, the Cassini Project, NASA's planetary project to place a spacecraft in orbit about Saturn, funded a study at the Jet Propulsion Laboratory (JPL) to identify rules for design and test of hardware required to function reliably in space for very long lifetimes. Twenty-nine subjects were considered comprising 130 specific rules related to long-life issues such as accelerated life testing, cycling of mechanical devices, selection and application of parts, semiconductor junction temperatures, and worst-case analysis for long life. The study was subsequently published as a JPL document. One major conclusion of the workshop was that unattended space missions extending out to 25 years or more are feasible.
Suitability of plastic-encapsulated solid-state electronic devices for use in spacecraft discussed. Conclusion of preliminary study was plasticencapsulated parts sufficiently reliable to be considered for use in lowcost equipment used at moderate temperature and low humidity. Useful to engineers as guides to testing or use of plastic encapsulated semiconductors in severe terrestrial environments.
A relatively new type of signal isolation based on Giant Magnetoresistive (GMR) technology was investigated for potential use in harsh temperature environments. Operational characteristics of the 2Mbps single channel, IL510-Series commercial-off-the-shelf (COTS) digital isolator chip was obtained under extreme temperature exposure and thermal cycling in the range of -190 C to +120 C. The isolator was evaluated in terms of its output signal delivery and stability, output rise (t(sub r)) and fall times (t(sub f)), and propagation delays at 50% level between input and output during low to high (t(sub PLH)) and high to low (t(sub PHL)) transitions. The device performed very well throughout the entire test temperature range as no significant changes occurred either in its function or in its output signal timing characteristics. The limited thermal cycling, which comprised of 12 cycles between -190 C and +120 C, also had no influence on its performance. In addition, the device packaging underwent no structural damage due to the extreme temperature exposure. These preliminary results indicate that this semiconductor chip has the potential for use in a temperature range that extends beyond its specified regime. Additional and more comprehensive testing, however, is required to establish its operation and reliability and to determine its suitability for long-term use in space exploration missions.
A photograph and a block diagram of the high-temperature probe station are shown. The system consists of the ceramic heater mounted on a NASA shuttle tile insulator, a direct current power supply, a personal-computer-based data acquisition and temperature controller, microwave probes, a microscope, and a network analyzer. The ability to perform microwave tests at high temperatures is becoming necessary. There is now a need for sensors and communication circuits that can operate at 500 C and above for aircraft engine development and monitoring during flight. To address this need, researchers have fabricated devices using wide bandgap semiconductors such as SiC with targeted operating temperatures of 500 to 600 C. However, the microwave properties of these devices often change drastically with temperature, so any designs that are intended to be used in such an environment must be characterized at high temperatures. For some reliability, lifetime, and direct-current testing, the device under test can be packaged and characterized in an oven. However, for RF and microwave measurements, it is usually not possible to establish a calibrated reference plane at the device terminals within a package. In addition, the characteristics of the package would vary over a 500 C temperature range, and this would have to be accounted for when the data were analyzed. A high temperature probe station allows circuits and devices to be characterized through on wafer measurements across a broad temperature range with known reference plane. The conventional, commercially available thermal wafer-probe stations that are used to evaluate microwave devices across a controlled temperature range have a typical upper limit of 200 C. Standalone thermal heating chucks are available with an extended upper temperature range of 300 to 400 C. To effectively characterize devices at temperatures up to and surpassing 500 C, Glenn researchers developed a custom probe station. In the past, custom probe stations have been developed to test devices under other extreme environments, such as cryogenic temperatures as low as 37 K. Similarly, this custom probe station was specifically modified for high-temperature use. It allows devices to be measured quickly and flexibly, without the use of wire bonds and test fixtures. The probe station is shown making scattering parameter measurements from 1 to 50 GHz with a Hewlett-Packard 8510C Network Analyzer. There is a half-wafer of silicon directly on top of the heater to provide a uniform heated platform for our sample. A quarter wafer of silicon carbide forms the substrate for our test circuit of several transmission lines.