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DOE OSTI2026

SPARTAN and IMPROVE Comparison Experiment (SPICE) Interim Campaign Report

SPICE (the SPARTAN and IMPROVE Comparison Experiment) aims to obtain and quantify comparisons between aerosol PM 2.5 mass concentration measurements from the University of Oklahoma (OU) Surface Particulate Matter Network (SPARTAN) station and the U.S. Environmental Protection Agency (EPA) Interagency Monitoring of Protected Visual Environments (IMPROVE) station hosted by the U.S. Department of Energy Atmospheric Radiation Measurement (ARM) User Facility at ARM’s Southern Great Plains (SGP) observatory in Oklahoma. Aerosols—both natural and anthropogenic—affect human populations in multiple ways. Much of ARM’s research focuses on how aerosols influence weather and climate through their optical and radiative effects, as well as their impacts on clouds and precipitation. However, aerosols also pose direct risks to humans and other organisms through inhalation, with the severity of health impacts depending on particle size, chemical composition, and duration of exposure. The IMPROVE network was established by the U.S. EPA to monitor air quality, including visible clarity as well as total and chemically speciated aerosol mass concentrations. The ARM SGP site hosts the IMPROVE SOGP station. Separately, the SPARTAN network operates a globally distributed set of stations similar to IMPROVE but with an emphasis on remote deployment and semi-autonomous operation for use beyond the borders of the United States (IMPROVE only operates within the U.S.). The University of Oklahoma operates a SPARTAN station. To establish confidence in the OU SPARTAN instrumentation and measurement protocol relative to the EPA-certified IMPROVE station, the OU SPARTAN station is currently deployed at SGP in close proximity to the IMPROVE SOGP station. The SPICE campaign was envisioned as a contiguous calendar-year effort for 2025 to capture seasonal variation in mass loading as well as composition. However, independent of the SPICE campaign, the SPARTAN network adopted a new filter construction part-way through the year, interrupting our contiguous data set. Thus, to obtain a contiguous data set with a uniform consistent configuration, SPICE desires an extension through 2026.

54 ENVIRONMENTAL SCIENCES↗

DOE OSTI2025

MLSPICE: Machine Learning based SPICE Modeling Platform for Power Magnetics

Electrical power converters are critical to a wide range of applications ranging from renewable integration to transportation electrification, and can be a key factor determining the size, weight, and efficiency of energy conversion systems. Magnetic components are typically the largest and least efficient components in power electronics. While there have been major strides in the modeling and analysis of power semiconductor devices and circuit simulations, the necessary advances in the design of power magnetics have lagged. In this project, we have transformed the modeling and design of power magnetics with machine learning enabled methods and catalyze simultaneous disruptive improvements for ML-based power electronics design tools. A fully automated open-source machine learning based magnetics modeling platform – the MagNet project - with innovations in full stack have been developed to greatly accelerate the design process and provide new insights to magnetic material and geometry design. The ARPA-E funded MagNet platform contains three major building blocks: 1) a ML-Integrated Data Acquisition System (MIDAS): a highly automated data acquisition testbed which is capable of measuring a large number of magnetic cores with a wide range of electrical circuit excitations; 2) a ML-integrated Core Loss Model (MICLM): a machine-learning trained modeling method for modeling the core loss and saturation effects of magnetic materials for arbitrary excitation waveforms; 3) ML-guided Magnetics SPICE Simulation Tool (PMSPICE): a fully integrated CAD tool which can simulate the magnetics in SPICE. It can help the designers to quickly model the linear and non-linear characteristics of magnetic components and evaluate their behavior in SPICE simulations. The developed MagNet system has fully demonstrated the proposed performance target and has been open sourced to the entire power electronics community to advance the modeling and design of power magnetics from many different angles.

36 MATERIALS SCIENCE↗

DOE OSTI2025

Parameter extraction for a SPICE model of an hTron superconducting thermal switch

Efficiently simulating large circuits is crucial to the development of superconducting nanowire-based electronics. However, current simulation tools for this technology are not adapted to the scaling of circuit size and complexity. We focus on the multilayered heater-nanocryotron (hTron), a promising superconducting nanowire-based switch used in applications such as superconducting nanowire single-photon detector readout. Previously, the hTron was modeled using traditional finite-element methods, which fall short in simulating systems at a larger scale. An empirical-based method would be better adapted to this task, enhancing both simulation speed and agreement with experimental data. In this work, we perform switching current and activation delay measurements on 17 hTron devices. We then develop a method for extracting physical fitting parameters used to characterize the devices. We build a SPICE behavioral model that reproduces the static and transient device behavior using these parameters, and validate it by comparing its performance to a model developed in prior work, showing an improvement in simulation time by several orders of magnitude. Furthermore, our model provides circuit designers with a tool to help understand the hTron’s behavior during all design stages, thus enabling broader use of the hTron across various new areas of application.

Caloritronics↗

DOE OSTI2024

Research at UC Berkeley on the SPICE and HeRALD Dark Matter Experiments (Technical Report for DE-SC0022354)

The McKinsey and Pyle groups have taken on the responsibility to complete a number of critical tasks necessary for the successful completion of the TESSERACT project planning phase. In particular: 1) Transition Edge Sensor testing, characterization, and electromagnetic noise mitigation; 2) Design and testing of the athermal phonon detectors along with vibrational noise characterization and mitigation; 3) Testing and characterization of prototype detectors using silica, sapphire, gallium arsenide, and superfluid helium as detector materials. This grant supported efforts of graduate student Roger Romani toward these goals.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

Integrating SPICE and pvlib for Advanced Modeling of PV String Power Losses

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Jost, Norman Robin [Sandia National Laboratories (↗

DOE OSTI2025

A Universal Augmentation Framework for Long-Range Electrostatics in Machine Learning Interatomic Potentials

Most current machine learning interatomic potentials (MLIPs) rely on short-range approximations, without explicit treatment of long-range electrostatics. To address this, we recently developed the Latent Ewald Summation (LES) method, which infers electrostatic interactions, polarization, and Born effective charges (BECs), just by learning from energy and force training data. Here, in this study, we present LES as a standalone library, compatible with any short-range MLIP, and demonstrate its integration with methods such as MACE, NequIP, Allegro, CACE, CHGNet, and UMA. We benchmark LES-enhanced models on distinct systems, including bulk water, polar dipeptides, and gold dimer adsorption on defective substrates, and show that LES not only captures correct electrostatics but also improves accuracy. Additionally, we scale LES to large and chemically diverse data by training MACELES-OFF on the SPICE set containing molecules and clusters, making a universal MLIP with electrostatics for organic systems, including biomolecules. MACELES-OFF is more accurate than its short-range counterpart (MACE-OFF) trained on the same data set, predicts dipoles and BECs reliably, and has better descriptions of bulk liquids. By enabling efficient long-range electrostatics without directly training on electrical properties, LES paves the way for electrostatic foundation MLIPs.

Kim, Dongjin [University of California, Berkeley, ↗

DOE OSTI2026

MIND-MAC: Multi-Level In-memory Quasi Non-Destructive MAC Operation in Compact 2T-nC FeRAM for Efficient DNN Accelerator

We present MIND-MAC, a compact 2T-nC FeRAM architecture that performs multi-level, quasi-non-destructive in-memory multiply–accumulate (MAC) for deep neural networks. By exploiting voltage-controlled partial domain switching in MFM capacitors and read-transistor amplification, the cell stores multi-bit weights and gates bit-serial inputs to produce an accumulated current on shared lines. We combine TCAD-extracted parasitics with experimentally calibrated ferroelectric models in SPICE to validate device-/circuit-level behavior, and validate multi-level sensing and QNRO with measurements on a fabricated 2T-3C test vehicle. An analytical system model maps MIND-MAC to a 6-GB main-memory in-memory compute (IMC) architecture and benchmarks VGG13 inference in 61.08 ms at 964.99 mJ. Results indicate high density, reduced rewrite overhead, and energy efficiency, positioning 2T-nC FeRAM as a promising IMC candidate for next-generation AI hardware.

36 MATERIALS SCIENCE↗

DOE OSTI2025

Single-Cell Universal Logic-in-Memory Using 2T-nC FeRAM: An Area and Energy-Efficient Approach for Bulk Bitwise Computation

This work presents a novel approach to configure 2T-nC ferroelectric RAM (FeRAM) for performing single cell logic-in-memory operations, highlighting its advantages in energy-efficient computation over conventional DRAM-based approaches. Unlike conventional 1T-1C dynamic RAM (DRAM), which incurs refresh overhead, 2T-nC FeRAM offers a promising alternative as a non-volatile memory solution with low energy consumption. Our key findings include the potential of quasi-nondestructive readout (QNRO) sensing in 2T-nC FeRAM for logic-in-memory (LiM) applications, demonstrating its inherent capability to perform inverting logic without requiring external modifications, a feature absent in traditional 1T-1C DRAM. We successfully implement the MINORITY function within a single cell of 2T-nC FeRAM, enabling universal NAND and NOR logic, validated through SPICE simulations and experimental data. Additionally, the research investigates the feasibility of 3D integration with 2T-nC FeRAM, showing substantial improvements in storage and computational density, facilitating bulk-bitwise computation. Our evaluation of eight real-world, data-intensive applications reveals that 2T-nC FeRAM achieves 2× higher performance and 2.5× lower energy consumption compared to DRAM. Furthermore, the thermal stability of stacked 2T-nC FeRAM is validated, confirming its reliable operation when integrated on a compute die. These findings emphasize the advantages of 2T-nC FeRAM for LiM, offering superior performance and energy efficiency over conventional DRAM.

36 MATERIALS SCIENCE↗

DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗

DOE OSTI2024

Nanosecond Transient Validation of Surge Arrester Models to Predict Electromagnetic Pulse Response

The impact of high-altitude electromagnetic pulse events on the electric grid is not fully understood, and validated modeling of mitigations, such as lightning surge arresters (LSAs) is necessary to predict the propagation of very fast transients on the grid. Experimental validation of high frequency models for surge arresters is an active area of research. Further, this article serves to experimentally validate a previously defined ZnO LSA model using four metal-oxide varistor pucks and nanosecond scale pulses to measure voltage and current responses. The SPICE circuit models of the pucks showed good predictability when compared to the measured arrester response when accounting for a testbed inductance of approximately 100 nH. Additionally, the comparatively high capacitance of low-profile arresters show a favorable response to high-speed transients that indicates the potential for effective electromagnetic pulse mitigation with future materials design.

42 ENGINEERING↗

DOE OSTI2024

Xyce™ Parallel Electronic Simulator Users' Guide (V.7.9)

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: • Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. • A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. • Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). • Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

42 ENGINEERING↗

DOE OSTI2024

Xyce™ Parallel Electronic Simulator (V.7.9) Release Notes

The Xyce™ Parallel Electronic Simulator has been written to support the simulation needs of Sandia National Laboratories’ electrical designers. Xyce™ is a SPICE-compatible simulator with the ability to solve extremely large circuit problems on large-scale parallel computing platforms, but also includes support for most popular parallel and serial computers. For up-to-date information not available at the time these notes were produced, please visit the Xyce™ web page at http://xyce.sandia.gov.

42 ENGINEERING↗

DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗

DOE OSTI2025

Xyce™ Parallel Electronic Simulator Version 7.10 Release Notes

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Xyce™ Parallel Electronic Simulator Users’ Guide, Version 7.10

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2026

DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77 K Using BSIM4

Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77 K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to operate at temperatures as low as 4 K making it a promising candidate for HEP applications. In this work, we characterize and model SKY130 low-threshold voltage transistors at 77 K, which is a temperature commonly used in modeling applications for liquid argon detectors. DC characteristic measurements were performed at both room temperature and liquid nitrogen temperature. We created a cryogenic modeling approach to produce a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77 K. The resulting model agrees with data at 77 K with an average error on the order of 20% (relative RMS) and shows no dependence on drain voltage. Due to the open-source nature of SKY130, we have made our models publicly available on Github. We hope this work will continue the trend for democratizing circuit design at cryogenic temperatures in high-energy physics by enabling open access to accurate cryogenic CMOS device models at 77 K.

Beall, F. [Texas U., Arlington]↗