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At least 19 records

Fault tolerant sequential machines

Memory cell fault tolerant sequential machine synthesis, considering masking feasibility and lower bounds on minimum redundancy

Meyer, J. F.

Feedback in sequential machine realizations.

A method is described for determining the realizability of a sequential machine with trigger or set-reset flip-flop memory elements when the feedback of the machine is given by a Boolean function. Feedbacks in several types of sequential machines with different memory elements are compared, showing the memory specifications allowing the realization of such machines.

Harlow, C. A.

A Computer Program for Simplifying Incompletely Specified Sequential Machines Using the Paull and Unger Technique

This report presents a description of a computer program mechanized to perform the Paull and Unger process of simplifying incompletely specified sequential machines. An understanding of the process, as given in Ref. 3, is a prerequisite to the use of the techniques presented in this report. This process has specific application in the design of asynchronous digital machines and was used in the design of operational support equipment for the Mariner 1966 central computer and sequencer. A typical sequential machine design problem is presented to show where the Paull and Unger process has application. A description of the Paull and Unger process together with a description of the computer algorithms used to develop the program mechanization are presented. Several examples are used to clarify the Paull and Unger process and the computer algorithms. Program flow diagrams, program listings, and a program user operating procedures are included as appendixes.

Ebersole, M. M.

Permutation codes for the state assignment of fault tolerant sequential machines

A new fault-tolerant state assignment method is suggested for synchronous sequential machines. It is assumed that the inputs are fault free and that for no input it is possible to reach all or most of the states, whose number may be fairly large. Error correcting codes for the state assignment are generated by permutations of a chosen linear code. A state assignment algorithm is developed and its computational complexity is estimated. Examples are given.

Chen, M.

Sequential behavior and its inherent tolerance to memory faults.

Representation of a memory fault of a sequential machine M by a function mu on the states of M and the result of the fault by an appropriately determined machine M(mu). Given some sequential behavior B, its inherent tolerance to memory faults can then be measured in terms of the minimum memory redundancy required to realize B with a state-assigned machine having fault tolerance type tau and fault tolerance level t. A behavior having maximum inherent tolerance is exhibited, and it is shown that behaviors of the same size can have different inherent tolerance.

Meyer, J. F.