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Results for “SEMICONDUCTOR DEVICE”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Reducing leakage current in semiconductor devices

A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals.

42 ENGINEERING↗
DOE OSTI2015

Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction

A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.

14 SOLAR ENERGY↗
DOE OSTI2020

Modeling Needs for Power Semiconductor Devices and Power Electronics Systems: Preprint

As energy systems move towards wide-spread electrification, penetration of power semiconductor devices and power electronics continues to grow at a rapid pace. This paper attempts to review the state of the art in power semiconductor modeling and the existing state of modeling in general when in it comes to design of devices and systems. The modeling needs for semiconductor devices vary depending on the end goal, and the level of abstraction needed towards model formulation also changes with the size and complexity of system to be designed. Finally, key aspects of thermal design and modeling for power electronics are also discussed.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

Conductive strip based mask for metallization of semiconductor devices

Methods of manufacturing a semiconductor device, and resulting semiconductor device are described. In an example, the method for manufacturing a semiconductor device include forming a semiconductor region and forming a metal seed region over the semiconductor region. The method can include placing a conductive strip over a first portion of the metal region, where the conductive strip is formed over the semiconductor region. The method can include bonding a contacting portion of the conductive strip to the first portion the metal region. The method can include etching a second portion of the metal region and where the conductive strip inhibits etching of the first portion of the metal region. In an example, the conductive strip can have a coating. In one example, the semiconductor device can be a solar cell.

14 SOLAR ENERGY↗
DOE OSTI2018

Thick Layered Semiconductor Devices with Water Top-Gates: High On–Off Ratio Field-Effect Transistors and Aqueous Sensors

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore deionized (DI) water as a solution top-gate for field-effect switching of layered semiconductors including SnS 2 , MoS 2 , and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on–off current ratios, near-ideal subthreshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels, where such control is difficult to realize with conventional back gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. In conclusion, DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Using a carbon vacancy reduction material to increase average carrier lifetime in a silicon carbide semiconductor device

A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Method for simultaneous modification of multiple semiconductor device features

Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2016

Memory effects in a Al/Ti:HfO{sub 2}/CuPc metal-oxide-semiconductor device

Metal oxide semiconductor structured organic memory device has been successfully fabricated. Ti doped hafnium oxide (Ti:HfO{sub 2}) nanoparticles has been fabricated by precipitation method and further calcinated at 800 °C. Copper phthalocyanine, a hole transporting material has been utilized as an organic semiconductor. The electrical properties of the fabricated device have been studied by measuring the current-voltage and capacitance-voltage characteristics. The amount of charge stored in the nanoparticles has been calculated by using flat band condition. This simple approach for fabricating MOS memory device has opens up opportunities for the development of next generation memory devices.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2016

Error-correction coding for hot-swapping semiconductor devices

A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the memory read operation is detected based on error-correction coding (ECC). The error is caused at least in part by the first semiconductor device having been removed. ECC is used to determine corrected data for the memory read operation.

42 ENGINEERING↗
DOE OSTI2022

Predicting failure parameters of semiconductor devices subjected to stress conditions

A method for predicting failure parameters of semiconductor devices can include receiving a set of data that includes (i) characteristics of a sample semiconductor device, and (ii) parameters characterizing a stress condition. The method further includes extracting a plurality of feature values from the set of data and inputting the plurality of feature values into a trained model executing on the one or more processors, wherein the trained model is configured according to an artificial intelligence (AI) algorithm based on a previous plurality of feature values, and wherein the trained model is operable to output a failure prediction based on the plurality of feature values. Further, the method includes generating, via the trained model, a predicted failure parameter of the sample semiconductor device due to the stress condition.

Ahmed, Moinuddin↗
DOE OSTI2014

Semiconductor device PN junction fabrication using optical processing of amorphous semiconductor material

Systems and methods for semiconductor device PN junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a P-N junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material.

14 SOLAR ENERGY↗
DOE OSTI2015

Theoretical discovery of stable structures of group III-V monolayers: The materials for semiconductor devices

Group III-V compounds are very important as the materials of semiconductor devices. Stable structures of the monolayers of group III-V binary compounds have been discovered by using first-principles calculations. The primitive unit cell of the discovered structures is a rectangle, which includes four group-III atoms and four group-V atoms. A group-III atom and its three nearest-neighbor group-V atoms are placed on the same plane; however, these connections are not the sp{sup 2} hybridization. The bond angles around the group-V atoms are less than the bond angle of sp{sup 3} hybridization. The discovered structure of GaP is an indirect transition semiconductor, while the discovered structures of GaAs, InP, and InAs are direct transition semiconductors. Therefore, the discovered structures of these compounds have the potential of the materials for semiconductor devices, for example, water splitting photocatalysts. The discovered structures may become the most stable structures of monolayers which consist of other materials.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Systems and methods for organic semiconductor devices with sputtered contact layers

Systems and methods for organic semiconductor devices with sputtered contact layers are provided. In one embodiment, an organic semiconductor device comprises: a first contact layer comprising a first sputter-deposited transparent conducting oxide; an electron transport layer interfacing with the first contact layer; a second contact layer comprising a second sputter-deposited transparent conducting oxide; a hole transport layer interfacing with the second contact layer; and an organic semiconductor active layer having a first side facing the electron transport layer and an opposing second side facing the hole transport layer; wherein either the electron transport layer or the hole transport layer comprises a buffering transport layer.

Hammond, Scott R.↗
DOE OSTI2024

Systems and methods for organic semiconductor devices with sputtered contact layers

Systems and methods for organic semiconductor devices with sputtered contact layers are provided. In one embodiment, an organic semiconductor device comprises: a first contact layer comprising a first sputter-deposited transparent conducting oxide; an electron transport layer interfacing with the first contact layer; a second contact layer comprising a second sputter-deposited transparent conducting oxide; a hole transport layer interfacing with the second contact layer; and an organic semiconductor active layer having a first side facing the electron transport layer and an opposing second side facing the hole transport layer; wherein either the electron transport layer or the hole transport layer comprises a buffering transport layer.

Hammond, Scott R.↗
DOE OSTI2020

Systems and methods for organic semiconductor devices with sputtered contact layers

Systems and methods for organic semiconductor devices with sputtered contact layers are provided. In one embodiment, an organic semiconductor device comprises: a first contact layer (140) comprising a first sputter-deposited transparent conducting oxide; an electron transport layer (130) interfacing with the first contact layer; a second contact layer (110) comprising a second sputter-deposited transparent conducting oxide; a hole transport layer interfacing with the second contact layer; and an organic semiconductor active layer (120) having a first side facing the electron transport layer and an opposing second side facing the hole transport layer; wherein either the electron transport layer or the hole transport layer comprises a buffering transport layer.

Hammond, Scott R.↗
DOE OSTI2014

Contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication

Methods for contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication are provided. In one embodiment, a method for fabricating an electrical semiconductor device comprises: a first step that includes gettering of impurities from a semiconductor wafer and forming a backsurface field; and a second step that includes forming a front contact for the semiconductor wafer, wherein the second step is performed after completion of the first step.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Semiconductor devices having a recessed electrode structure

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗