Noise behavior in semiconductor devices.
Semiconductor noise behavior as key to transistor device design
SEMICONDUCTOR DEVICE↗
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Reducing leakage current in semiconductor devices
A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals.
42 ENGINEERING↗
Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction
A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.
14 SOLAR ENERGY↗
Semiconductor device having a lateral transistor device and an inverter that includes the semiconductor device
In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.
Häberlen, Oliver↗
Modeling Needs for Power Semiconductor Devices and Power Electronics Systems: Preprint
As energy systems move towards wide-spread electrification, penetration of power semiconductor devices and power electronics continues to grow at a rapid pace. This paper attempts to review the state of the art in power semiconductor modeling and the existing state of modeling in general when in it comes to design of devices and systems. The modeling needs for semiconductor devices vary depending on the end goal, and the level of abstraction needed towards model formulation also changes with the size and complexity of system to be designed. Finally, key aspects of thermal design and modeling for power electronics are also discussed.
24 POWER TRANSMISSION AND DISTRIBUTION↗
Porous silicon carbide (SiC) semiconductor device
A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.
Shor, Joseph S.↗
Conductive strip based mask for metallization of semiconductor devices
Methods of manufacturing a semiconductor device, and resulting semiconductor device are described. In an example, the method for manufacturing a semiconductor device include forming a semiconductor region and forming a metal seed region over the semiconductor region. The method can include placing a conductive strip over a first portion of the metal region, where the conductive strip is formed over the semiconductor region. The method can include bonding a contacting portion of the conductive strip to the first portion the metal region. The method can include etching a second portion of the metal region and where the conductive strip inhibits etching of the first portion of the metal region. In an example, the conductive strip can have a coating. In one example, the semiconductor device can be a solar cell.
14 SOLAR ENERGY↗
Thick Layered Semiconductor Devices with Water Top-Gates: High On–Off Ratio Field-Effect Transistors and Aqueous Sensors
Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore deionized (DI) water as a solution top-gate for field-effect switching of layered semiconductors including SnS 2 , MoS 2 , and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on–off current ratios, near-ideal subthreshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels, where such control is difficult to realize with conventional back gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. In conclusion, DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.
36 MATERIALS SCIENCE↗
Method of making a semiconductor device assembly
The invention is a semiconductor device assembly and method of making the same. A mounting plate has positioning means for positioning the plate relative to a header, a first mounting surface of the plate is attached to the header and a semiconductor device is attached to a second mounting surface of the mounting plate. The assembly is made by forming the mounting plate, positioning the mounting plate relative to the header by the positioning means, attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. Another method of making the assembly is by defining and etching a mounting plate and attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. This assembly and process provides an efficient means for mounting semiconductor devices and in particular electro-optic devices such as lasers.
Dholakia, Anil R.↗
Using a carbon vacancy reduction material to increase average carrier lifetime in a silicon carbide semiconductor device
A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.
36 MATERIALS SCIENCE↗
Superior photoengraving process for semiconductor devices
Photoengraving process for semiconductor devices
SEMICONDUCTOR DEVICE↗
Reliability of Compound Semiconductor Devices for Space Applications
Application of Semiconductor devices in high reliability space systems requires a thorough understanding of the reliability and failure mechanisms associated with the selected devices.
semiconductor device↗
Semiconductor device assembly and method of making same
The invention is a semiconductor device assembly and method of making the same. A mounting plate has positioning means for positioning the plate relative to a header, a first mounting surface of the plate is attached to the header and a semiconductor device is attached to a second mounting surface of the mounting plate. The assembly is made by forming the mounting plate, positioning the mounting plate relative to the header by the positioning means, attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. Another method of making the assembly is by defining and etching a mounting plate and attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. This assembly and process provides an efficient means for mounting semiconductor devices and in particular electro-optic devices such as lasers.
Dholakia, Anil R.↗
Method for simultaneous modification of multiple semiconductor device features
Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
A Thermal and Electrical Analysis of Power Semiconductor Devices
The state-of-art power semiconductor devices require a thorough understanding of the thermal behavior for these devices. Traditional thermal analysis have (1) failed to account for the thermo-electrical interaction which is significant for power semiconductor devices operating at high temperature, and (2) failed to account for the thermal interactions among all the levels involved in, from the entire device to the gate micro-structure. Furthermore there is a lack of quantitative studies of the thermal breakdown phenomenon which is one of the major failure mechanisms for power electronics. This research work is directed towards addressing. Using a coupled thermal and electrical simulation, in which the drift-diffusion equations for the semiconductor and the energy equation for temperature are solved simultaneously, the thermo-electrical interactions at the micron scale of various junction structures are thoroughly investigated. The optimization of gate structure designs and doping designs is then addressed. An iterative numerical procedure which incorporates the thermal analysis at the device, chip and junction levels of the power device is proposed for the first time and utilized in a BJT power semiconductor device. In this procedure, interactions of different levels are fully considered. The thermal stability issue is studied both analytically and numerically in this research work in order to understand the mechanism for thermal breakdown.
Vafai, Kambiz↗
Compound Semiconductor Devices for Space Applications
Application of semiconductor devices in high reliability space systems requires a thorough understanding of the reliability and failure mechanisms associated with the selected devices. This paper provides a description of the reliability and qualification issues related to the application of compound semiconductor devices in critical space systems. A discussion of common failure mechanisms, radiation effects and other reliability concerns is provided along with a discussion of methods for technology qualification for high reliability space applications.
Kayali, Sammy↗
Memory effects in a Al/Ti:HfO{sub 2}/CuPc metal-oxide-semiconductor device
Metal oxide semiconductor structured organic memory device has been successfully fabricated. Ti doped hafnium oxide (Ti:HfO{sub 2}) nanoparticles has been fabricated by precipitation method and further calcinated at 800 °C. Copper phthalocyanine, a hole transporting material has been utilized as an organic semiconductor. The electrical properties of the fabricated device have been studied by measuring the current-voltage and capacitance-voltage characteristics. The amount of charge stored in the nanoparticles has been calculated by using flat band condition. This simple approach for fabricating MOS memory device has opens up opportunities for the development of next generation memory devices.
77 NANOSCIENCE AND NANOTECHNOLOGY↗
Error-correction coding for hot-swapping semiconductor devices
A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the memory read operation is detected based on error-correction coding (ECC). The error is caused at least in part by the first semiconductor device having been removed. ECC is used to determine corrected data for the memory read operation.
42 ENGINEERING↗