Orthogonal Functions Based SAR Processing Algorithm for Processing Spaceborne Spotlingt SAR Data
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The chirp scaling SAR processing algorithm is both accurate and efficient. Successful implementation requires proper selection of the interval of output samples, which is a function of the chirp interval, signal sampling rate, and signal bandwidth. Analysis indicates that for both airborne and spaceborne SAR applications in the slant range domain a linear chirp scaling is sufficient. To perform nonlinear interpolation process such as to output ground range SAR images, one can use a nonlinear chirp scaling interpolator presented in this paper.
This paper provides an assessment of the on-board SAR processing technology for Eos-type missions. The proposed Eos SAR sensor and flight data system are introduced, and the SAR processing requirements are described. The SAR on-board SAR processor architecture selection is discussed, and a baseline processor architecture using a frequency-domain processor for range correlation and a modular fault-tolerant VLSI time-domain parallel array for azimuth correlation are described. The mass storage and VLSI technologies needed for implementing the proposed SAR processing are assessed. It is shown that acceptable processor power and mass characteristics should be feasible for Eos-type applications. A proposed development strategy for the on-board SAR processor is presented.
The launch of spaceborne SARs during the 1980's is discussed. The satellite SARs require high quality and high throughput ground processors. Compression ratios in range and azimuth of greater than 500 and 150 respectively lead to frequency domain processing and data computation rates in excess of 2000 million real operations per second for C-band SARs under consideration. Various hardware architectures are examined and two promising candidates and proceeds to recommend a fast, programmable hardware architecture for spaceborne SAR processing are selected. Modularity and programmability are introduced as desirable attributes for the purpose of HTSP hardware selection.
A new digital processing algorithm based on the fast polynomial transform is developed for producing images from Synthetic Aperture Radar data. This algorithm enables the computation of the two dimensional cyclic correlation of the raw echo data with the impulse response of a point target, thereby reducing distortions inherent in one dimensional transforms. This SAR processing technique was evaluated on a general-purpose computer and an actual Seasat SAR image was produced. However, regular production runs will require a dedicated facility. It is expected that such a new SAR processing algorithm could provide the basis for a real-time SAR correlator implementation in the Deep Space Network.
A new digital processing algorithm based on the fast polynomial transform is developed for producing images from Synthetic Aperture Radar data. This algorithm enables the computation of the two dimensional cyclic correlation of the raw echo data with the impulse response of a point target, thereby reducing distortions inherent in one dimensional transforms. This SAR processing technique was evaluated on a general-purpose computer and an actual Seasat SAR image was produced. However, regular production runs will require a dedicated facility. It is expected that such a new SAR processing algorithm could provide the basis for a real-time SAR correlator implementation in the Deep Space Network. Previously announced in STAR as N82-11295
A high quality spotlight SAR processing algorithm is presented. In this algorithm, subband images of the radar illuminated spot are pocessed using well known strip mode processing algorithms.
The processing of synthetic aperture radar (SAR) signals using the massively parallel processor (MPP) is discussed. The fast Fourier transform convolution procedures employed in the algorithms are described. The MPP architecture comprises an array unit (ARU) which processes arrays of data; an array control unit which controls the operation of the ARU and performs scalar arithmetic; a program and data management unit which controls the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE). Two-by-four surarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory which buffers and permutes data flowing with the system. Efficient SAR processing is achieved via ARU communication paths and SM data manipulation. Real time processing capability can be realized via a multiple ARU, multiple SM configuration.
We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.
Technique for processing synthetic-aperture-radar (SAR) signals exploits fact that center frequency of frequency channel of data being processed linked directly to squint angle and to azimuth angle. Also exploits fact in multilook SAR data processing, total bandwidth of each SAR polarization channel divided into N (typically, N = 16) equal frequency channels, data in each of which processed separately. Technique has yielded data on directionality of radar back scatter from agricultural fields.
The SAR (synthetic-aperture radar) data-processing algorithm to be used for the Magellan mission is described. Radar system design, SAR data characteristics, and hardware (H/W) constraints, which are critical to the processing algorithm design, are highlighted. Data flow and the H/W architecture are given to show the real-time data processing capability. Simulation results obtained from processing the synthetic point-target echos are presented to demonstrate the performance of the processing algorithm.
The algorithms and implementation of an integrated SAR processor designed to process multi-frequency SAR data from either polarimetric, interferometric or mixed mode (a combination of polarimetric and interferometric modes) SAR systems is described.
The algorithms and implementation of an integrated SAR processor designed to process multi-frequency SAR data from either polarimetric, interferometric or mixed mode (a combination of polarimetric and interferometric modes) SAR systems is described.
"Instant" photographic film based on semisynthetic retinal pigment bacteriorhodopsin proposed for optical processing of synthetic-aperture-radar (SAR) signals. Input image recorded on film by laser operating at writing wavelength of bacteriorhodopsin, and output image recorded on computer by standard frame-grabber. Because it requires no chemical development, enables processing in nearly real time. Fast response and high resolution well suited for application. Film reusable, with concomitant reduction in cost of SAR processing.
A simplified model for the SAR imaging problem is presented. The model is based on the geometry of the SAR system. Using this model an expression for the entire phase history of the received SAR signal is formulated. From the phase history, it is shown that the range and the azimuth coordinates for a point target image can be obtained by processing the phase information during the intrapulse and interpulse periods respectively. An architecture for a VLSI implementation for the SAR signal processor is presented which generates images in real time. The architecture uses a small number of chips, a new correlation processor, and an efficient azimuth correlation process.
A highly programmable, land based, real time synthetic aperture radar (SAR) processor requiring a processed pixel rate of 2.75 MHz or more in a four look system was designed. Variations in range and azimuth compression, number of looks, range swath, range migration and SR mode were specified. Alternative range and azimuth processing algorithms were examined in conjunction with projected integrated circuit, digital architecture, and software technologies. The advaced digital SAR processor (ADSP) employs an FFT convolver algorithm for both range and azimuth processing in a parallel architecture configuration. Algorithm performace comparisons, design system design, implementation tradeoffs and the results of a supporting survey of integrated circuit and digital architecture technologies are reported. Cost tradeoffs and projections with alternate implementation plans are presented.
The NASA ISRO Synthetic Aperture Radar (NISAR) mission will redefine the future of earth science in terms of both the quality as well as the quantity of data that will be downlinked daily. The current software architecture used to process this data is the InSAR Scientific Computing Environment (ISCE), a powerful and modular platform that applies a combination of novel and legacy processing modules to many sources of SAR data. Until recently, this architecture could process most images in a reasonable amount of time; however in the case of the NISAR mission (where the daily influx as well as the size of the images themselves are significantly larger) the current architecture can take hours to process even a single image. This paper explores new efforts to use a Graphics Processing Unit (GPU) to accelerate one of the processing modules to achieve unprecedented runtimes with no loss in precision, potentially setting a new standard in radar processing in the world of “Big Data”.
Exact transfer function, ETF, is two-dimensional transfer function that constitutes basis of improved frequency-domain-convolution algorithm for processing synthetic-aperture-radar, SAR data. ETF incorporates terms that account for Doppler effect of motion of radar relative to scanned ground area and for antenna squint angle. Algorithm based on ETF outperforms others.