SEARCH · Engineering Papers

Results for “Pulsed Phase-locked Loop”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

3 records

All sources NASA NTRS DOE OSTI

DOE OSTI2025

An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA

In TDC testing and timing system implementations, it is often necessary to generate signal pulses with finely adjustable time intervals. In delay cell–based schemes, the adjustment resolution is constrained by the propagation delay of the cells—typically 15–20 ps per step—and is sensitive to temperature and supply voltage variations. This document presents a fully digital approach that uses two vernier clocks, generated by two stages of cascaded phase-locked loops (PLLs) with a slight frequency difference, to achieve adjustable timing intervals through accumulated phase differences. The scheme was validated on two families of low-cost FPGA devices, achieving adjustable step sizes of 0.67 ps and 0.97 ps.

Wu, Jin-yuan [Fermilab] (ORCID:0000000344329521)↗

DOE OSTI2021

Compact, All-PM Fiber Integrated and Alignment-Free Ultrafast Yb:Fiber NALM Laser With Sub-Femtosecond Timing Jitter

We report a simple and compact design of a dispersion compensated mode-locked Yb:fiber oscillator based on a nonlinear amplifying loop mirror (NALM). The fully polarization maintaining (PM) fiber integrated laser features a chirped fiber Bragg grating (CFBG) for dispersion compensation and a fiber integrated compact non-reciprocal phase bias device, which is alignment-free. The main design parameters were determined by numerically simulating the pulse evolution in the oscillator and by analyzing their impact on the laser performance. Experimentally, we achieved an 88 fs compressed pulse duration with sub-fs timing jitter at 54 MHz repetition rate and 51 mW of output power with 5.5×10 -5 [20 Hz, 1 MHz] integrated relative intensity noise (RIN). Furthermore, we demonstrate tight phase-locking of the laser's carrier-envelope offset frequency ( fceo ) to a stable radio frequency (RF) reference and of one frequency comb tooth to a stable optical reference at 291 THz.

47 OTHER INSTRUMENTATION↗

DOE OSTI2022

Carrier and sampling frequency offset estimation for RF communication with crystal-less nodes

When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

Kim, Hun-Seok↗