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At least 19 records

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibit a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

Performance Analysis Tool for HPC and Big Data Applications on Scientific Clusters

Big data is prevalent in HPC computing. Many HPC projects rely on complex workflows to analyze terabytes or petabytes of data. These workflows often require running over thousands of CPU cores and performing simultaneous data accesses, data movements, and computation. It is challenging to analyze the performance involving terabytes or petabytes of workflow data or measurement data of the executions, from complex workflows over a large number of nodes and multiple parallel task executions. To help identify performance bottlenecks or debug the performance issues in large-scale scientific applications and scientific clusters, we have developed a performance analysis framework, using state-ofthe- art open-source big data processing tools. Our tool can ingest system logs and application performance measurements to extract key performance features, and apply the most sophisticated statistical tools and data mining methods on the performance data. It utilizes an efficient data processing engine to allow users to interactively analyze a large amount of different types of logs and measurements. To illustrate the functionality of the big data analysis framework, we conduct case studies on the workflows from an astronomy project known as the Palomar Transient Factory (PTF) and the job logs from the genome analysis scientific cluster. Our study processed many terabytes of system logs and application performance measurements collected on the HPC systems at NERSC. The implementation of our tool is generic enough to be used for analyzing the performance of other HPC systems and Big Data workows.

97 MATHEMATICS AND COMPUTING↗

Performance Analysis, Design Considerations, and Applications of Extreme-Scale In Situ Infrastructures

A key trend facing extreme-scale computational science is the widening gap between computational and I/O rates, and the challenge that follows is how to best gain insight from simulation data when it is increasingly impractical to save it to persistent storage for subsequent visual exploration and analysis. One approach to this challenge is centered around the idea of in situ processing, where visualization and analysis processing is performed while data is still resident in memory. This paper examines several key design and performance issues related to the idea of in situ processing at extreme scale on modern platforms: Scalability, overhead, performance measurement and analysis, comparison and contrast with a traditional post hoc approach, and interfacing with simulation codes. We illustrate these principles in practice with studies, conducted on large-scale HPC platforms, that include a miniapplication and multiple science application codes, one of which demonstrates in situ methods in use at greater than 1M-way concurrency.

Ayachit, Utkarsh↗

The Role of Sensitivity Analysis in the Building Performance Analysis: A Critical Review

A building system is highly nonlinear and commonly includes a variety of parameters ranging from the architectural design to the building mechanical and energy system. Serving as a powerful tool to understand the complicated building system, sensitivity analysis (SA) has been receiving increasing attention in the recent decade. This review paper focused on the application of SA in the building performance analysis (BPA). First, the existing review papers on the application of SA for BPA were briefly reviewed and summarized. Then, a large amount of recent SA case studies in BPA were reviewed. The critical information regarding the implementation of a SA, such as the sampling method, the SA method, etc., were extracted and summarized. Next, an extensive analysis was performed to evaluate the role of the SA in the BPA. This includes: 1) The typical selection of the input and output parameters for the SA were visualized; 2) The uncertainty level and sampling strategies for the input parameters were investigated; 3) The principles, benefits, and drawbacks of the SA methods were analyzed and summarized; and 4) The various tools used in the SA, including the simulation software, sampling tools, and SA tools were introduced to facilitate the practitioners. Lastly, several conclusions were summarized on the role of the SA in the BPA. Suggestions were also provided to offer practical solutions to the current challenges.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Novel features and GPU performance analysis for EM particle transport in the Celeritas code

Celeritas is a new computational transport code designed for high-performance simulation of high-energy physics detectors. This work describes some of its current capabilities and the design choices that enable the rapid development of efficient on-device physics. The abstractions that underpin the code design facilitate low-level performance tweaks that require no changes to the higher-level physics code. We evaluate a set of independent changes that together yield an almost 40% speedup over the original GPU code for a net performance increase of 220× for a single GPU over a single CPU running 8.4M tracks on a small demonstration physics app.

Johnson, Seth R.↗

Metallic Fuel Performance Analysis for the European Sodium Fast Reactor (ESFR-SIMPLE): Analysis of metallic fuel performance using SAS4A/SASSYS-1 $-$ MFUEL

The European Sodium Fast Reactor - Safety by Innovative Monitoring, Power Level flexibility and Experimental research (ESFR-SIMPLE) project was initiated in 2022 and includes assessment of a metallic-fueled version of the ESFR concept. Argonne National Laboratory (ANL) has been partnering with the ESFR-SIMPLE project to share its expertise on metallic fueled SFR designs and support some of its analysis. This report focuses on metallic fuel behavior analysis for ESFR-SIMPLE design conditions under base irradiation and transients (ULOF and UTOP).

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

TOKIO on ClusterStor: Connecting Standard Tools to Enable Holistic I/O Performance Analysis

At present, I/O performance analysis requires different tools to characterize individual components of the I/O subsystem, and institutional I/O expertise is relied upon to translate these disparate data into an integrated view of application performance. This process is labor-intensive and not sustainable as the storage hierarchy deepens and system complexity increases. To address this growing disparity, we have developed the Total Knowledge of I/O (TOKIO) framework to combine the insights from existing component-level monitoring tools and provide a holistic view of performance across the entire I/O stack. A reference implementation of TOKIO, pytokio, is presented here. Using monitoring tools included with Cray XC and ClusterStor systems alongside commonly deployed community-supported tools, we demonstrate how pytokio provides a lightweight foundation for holistic I/O performance analyses on two Cray XC systems deployed at different HPC centers. We present results from integrated analyses that allow users to quantify the degree of I/O contention that affected their jobs and probabilistically identify unhealthy storage devices that impacted their performance.We also apply pytokio to inspect the utilization of NERSC’s DataWarp burst buffer and demonstrate how pytokio can be used to identify users and applications who may stand to benefit most from migrating their workloads from Lustre to the burst buffer.

Lockwood, Glenn K.↗

PAPI software-defined events for in-depth performance analysis

The methodology and standardization layer provided by the Performance Application Programming Interface (PAPI) has played a vital role in application profiling for almost two decades. It has enabled sophisticated performance analysis tool designers and performance-conscious scientists to gain insights into their applications by simply instrumenting their code using a handful of PAPI functions that “just work” across different hardware components. In the past, PAPI development had focused primarily on hardware-specific performance metrics. However, the rapidly increasing complexity of software infrastructure poses new measurement and analysis challenges for the developers of large-scale applications. In particular, acquiring information regarding the behavior of libraries and runtimes—used by scientific applications—requires low-level binary instrumentation, or APIs specific to each library and runtime. No uniform API for monitoring events that originate from inside the software stack has emerged. In this article, we present our efforts to extend PAPI’s role so that it becomes the de facto standard for exposing performance-critical events, which we refer to as software-defined events (SDEs), from different software layers. Upgrading PAPI with SDEs enables monitoring of both types of performance events—hardware- and software-related events—in a uniform way, through the same consistent PAPI. The goal of this article is threefold. First, we motivate the need for SDEs and describe our design decisions regarding the functionality we offer through PAPI’s new SDE interface. Second, we illustrate how SDEs can be utilized by different software packages, specifically, by showcasing their use in the numerical linear algebra library MAGMA-Sparse, the tensor algebra library TAMM that is part of the NWChem suite, and the compiler-based performance analysis tool Byfl. Third, we provide a performance analysis of the overhead that results from monitoring SDEs and discuss the trade-offs between overhead and functionality.

Jagode, Heike↗

Performance Analysis of Deep Learning Workloads on Leading-edge Systems

This work examines the performance of leading-edge systems designed for machine learning computing, including the NVIDIA DGX-2, Amazon Web Services (AWS) P3, IBM Power System Accelerated Compute Server AC922, and a consumer-grade Exxact TensorEX TS4 GPU server. Representative deep learning workloads from the fields of computer vision and natural language processing are the focus of the analysis. Performance analysis is performed along with a number of important dimensions. Performance of the communication interconnects and large and high-throughput deep learning models are considered. Different potential use models for the systems as standalone and in the cloud also are examined. The effect of various optimization of the deep learning models and system configurations is included in the analysis.

97 MATHEMATICS AND COMPUTING↗

Traveler: Navigating Task Parallel Traces for Performance Analysis

Understanding the behavior of software in execution is a key step in identifying and fixing performance issues. This is especially important in high performance computing contexts where even minor performance tweaks can translate into large savings in terms of computational resource use. To aid performance analysis, developers may collect an execution trace —a chronological log of program activity during execution. As traces represent the full history, developers can discover a wide array of possibly previously unknown performance issues, making them an important artifact for exploratory performance analysis. However, interactive trace visualization is difficult due to issues of data size and complexity of meaning. Traces represent nanosecond-level events across many parallel processes, meaning the collected data is often large and difficult to explore. The rise of asynchronous task parallel programming paradigms complicates the relation between events and their probable cause. Here, to address these challenges, we conduct a continuing design study in collaboration with high performance computing researchers. We develop diverse and hierarchical ways to navigate and represent execution trace data in support of their trace analysis tasks. Through an iterative design process, we developed Traveler , an integrated visualization platform for task parallel traces. Traveler provides multiple linked interfaces to help navigate trace data from multiple contexts. We evaluate the utility of Traveler through feedback from users and a case study, finding that integrating multiple modes of navigation in our design supported performance analysis tasks and led to the discovery of previously unknown behavior in a distributed array library.

97 MATHEMATICS AND COMPUTING↗

Internet Performance Analysis of South Asian Countries Using End-to-End Internet Performance Measurements

Internet performance is highly correlated with key economic development metrics of a region. According to World Bank, the economic growth of a country increases 1.3% with a 10% increase in the speed of the Internet. Therefore, it is necessary to monitor and understand the performance of the Internet links in the region. It helps to figure out the infrastructural inefficiencies, poor resource allocation, and routing issues in the region. Moreover, it provides healthy suggestions for future upgrades. Therefore, the objective of this paper is to understand the Internet performance and routing infrastructure of South Asian countries in comparison to the developed world and neighboring countries using end-to-end Internet performance measurements. The South Asian countries comprise nearly 32% of the Internet users in Asia and nearly 16% of the world. The Internet performance metrics in the region are collected through the PingER framework. The framework is developed by the SLAC National Accelerator Laboratory, USA and is running for the last 20 years. PingER has 16 monitoring nodes in the region, and in the last year PingER monitors about 40 sites in South Asia using the ubiquitous ping facility. The collected data is used to estimate the key Internet performance metrics of South Asian countries. The performance metrics are compared with the neighboring countries and the developed world. Particularly, the TCP throughput of the countries is also correlated with different development indices. Further, worldwide Internet connectivity and routing patterns of the countries are investigated to figure out the inconsistencies in the region. Furthermore, the performance analysis revealed that the South Asia region is 7-10 years behind the developed regions of North America (USA and Canada), Europe, and East Asia.

97 MATHEMATICS AND COMPUTING↗

Empirical Performance Analysis of HPC Applications with Portable Hardware Counter Metrics [Thesis]

In this dissertation, we demonstrate that it is possible to develop methods of empirical hardware-counter-based performance analysis for scientific applications running on diverse types of CPUs. Although hardware counters have been used in performance analysis for at least 30 years, the methods used are still limited to particular CPU vendors or even particular generations of CPUs from the same vendor. Our motivating hypothesis is that hardware counter-based measurements could be developed to provide consistent performance information on diverse CPU types. This dissertation proves the hypothesis was correct by demonstrating one such set of metrics.

97 MATHEMATICS AND COMPUTING↗