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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Pushing the limits of NAND technology scaling with ferroelectrics

Artificial intelligence (AI) continues to drive transformative advancements across various industries. The data-intensive nature of AI training (and inferencing) has resulted in the generation of unprecedented volumes of data with machine-generated content surpassing human-generated data by more than 100-fold in 2025. Efficiently managing this data influx necessitates advanced digital storage technologies. However, traditional NAND flash memory, which is critical for supporting data flows in AI systems—alongside high-bandwidth memory, for AI training—faces fundamental scaling limitations as it approaches the 1000-layer milestone, encompassing more than 40 trillion transistors. This article delves into the potential of hafnia-based ferroelectric materials as a breakthrough solution to these challenges. Recent advancements indicate that the intrinsic limitations of ferroelectric field-effect transistors (FEFETs) can be mitigated through material and device-level engineering. These advancements enable FEFETs to meet the stringent density, reliability, and scalability requirements of future three-dimensional NAND technology. The role of ferroelectrics in addressing NAND scaling challenges and expanding storage capabilities presents a promising avenue for meeting the storage demands of the AI-driven era.

3D NAND↗
DOE OSTI2025

Securing 3D NAND Without Density Loss via In-Situ Encryption Using a Single Transistor XOR Cell

In this article, we push lightweight XOR-based in-situ encryption to extreme density by proposing a singletransistor XOR memory cell and applying it to 3D NAND, enabling secure data storage without density loss. Using a ferroelectric field-effect transistor (FeFET) as an example technology, we demonstrate that: i) a single-transistor memory can realize the XOR function by exploiting the ability to charge the source and drain separately and control current flow direction, eliminating the need for conventional encrypted cells that rely on complementary devices; ii) with a XOR-based cipher, encryption and decryption can be mapped to in-situ array operations, where ciphertext is stored as the threshold voltage (VTH) states of FeFETs in a NAND string, and decryption is achieved through read operations using key-dependent complementary source/drain bias; iii) the proposed technique is scalable to multi-level cell (MLC) storage by encrypting and decrypting data bit by bit; iv) using an integrated NAND FeFET array, we experimentally demonstrate encryption and decryption operations for both single-level cell (SLC) and MLC storage; v) systemlevel benchmarking shows that the proposed technique achieves 48× and 278× improvements in encryption and decryption throughput, respectively, compared to AES.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Charge Trap Layer Supercharging for Improved Bit Reliability in 3-D NAND Flash Under Proton Irradiation

Single-event upset (SEU) cross sections are reduced in 176-layer charge trap (CT) 3-D nand devices under proton irradiation when multiple write operations are applied sequentially without the typical erase-before-write. Here, this effect is observed for multiple data patterns and in both single-level cell (SLC) and triple-level cell (TLC) operating modes. SEU cross section calculation methodologies are discussed for highly scaled 3-D devices both with and without the application of rewrites, and potential implications for long-term endurance effects are proposed.

Breeding, Matthew Luel [Sandia National Laboratori↗
DOE OSTI2024

Superionic fluoride gate dielectrics with low diffusion barrier for two-dimensional electronics

Exploration of new dielectrics with a large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near the breakdown limit. Here, to address this looming challenge, we demonstrate that rare-earth metal fluorides with extremely low ion migration barriers can generally exhibit an excellent capacitive coupling over 20 μF cm -2 (with an equivalent oxide thickness of ~0.15 nm and a large effective dielectric constant near 30) and great compatibility with scalable device manufacturing processes. Such a static dielectric capability of superionic fluorides is exemplified by MoS 2 transistors exhibiting high on/off current ratios over 10 8 , ultralow subthreshold swing of 65 mV dec -1 and ultralow leakage current density of ~10 -6 A cm -2 . Therefore, the fluoride-gated logic inverters can achieve notably higher static voltage gain values (surpassing ~167) compared with a conventional dielectric. Furthermore, the application of fluoride gating enables the demonstration of NAND, NOR, AND and OR logic circuits with low static energy consumption. In particular, the superconductor–insulator transition at the clean-limit Bi 2 Sr 2 CaCu 2 O 8+δ can also be realized through fluoride gating. In conclusion, our findings highlight fluoride dielectrics as a pioneering platform for advanced electronic applications and for tailoring emergent electronic states in condensed matter.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

On the Origin of Holes During Polarization Reset in Floating Body Ferroelectric FETs Towards Improving Switching Efficiency

In this article, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of device with growing interests due to added functionalities and improved reliabilities. Using fully-depleted silicon-on-insulator (FDSOI) FeFET as a classical example, we demonstrate that: 1) without hole generation mechanisms, floating body FeFETs during reset is simply a capacitor divider, with negligible ferroelectric voltage drop for switching; ii) Band-to-band-tunneling (BTBT) around gate-to-S/D overlap even with zero drain bias generates holes to facilitate the reset in FDSOI FeFET, though at a slower speed and hold the reset state; iii) With scaling, S/D inner fringe field can enable fast reset, thus offering a potential efficiency boost approach; iv) a compact FDSOI FeFET model is developed that can capture the BTBT effect and reproduce the observed behaviors; v) the reset mechanism is also validated in a NAND string composed of FDSOI FeFETs, demonstrating its relevant applications. These insights show the strategies in improving reset efficiency, i.e., enhanced BTBT and inner fringe field.

42 ENGINEERING↗
DOE OSTI2025

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗
DOE OSTI2025

Single-Cell Universal Logic-in-Memory Using 2T-nC FeRAM: An Area and Energy-Efficient Approach for Bulk Bitwise Computation

This work presents a novel approach to configure 2T-nC ferroelectric RAM (FeRAM) for performing single cell logic-in-memory operations, highlighting its advantages in energy-efficient computation over conventional DRAM-based approaches. Unlike conventional 1T-1C dynamic RAM (DRAM), which incurs refresh overhead, 2T-nC FeRAM offers a promising alternative as a non-volatile memory solution with low energy consumption. Our key findings include the potential of quasi-nondestructive readout (QNRO) sensing in 2T-nC FeRAM for logic-in-memory (LiM) applications, demonstrating its inherent capability to perform inverting logic without requiring external modifications, a feature absent in traditional 1T-1C DRAM. We successfully implement the MINORITY function within a single cell of 2T-nC FeRAM, enabling universal NAND and NOR logic, validated through SPICE simulations and experimental data. Additionally, the research investigates the feasibility of 3D integration with 2T-nC FeRAM, showing substantial improvements in storage and computational density, facilitating bulk-bitwise computation. Our evaluation of eight real-world, data-intensive applications reveals that 2T-nC FeRAM achieves 2× higher performance and 2.5× lower energy consumption compared to DRAM. Furthermore, the thermal stability of stacked 2T-nC FeRAM is validated, confirming its reliable operation when integrated on a compute die. These findings emphasize the advantages of 2T-nC FeRAM for LiM, offering superior performance and energy efficiency over conventional DRAM.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Low-temperature etching of silicon oxide and silicon nitride with hydrogen fluoride

Etching of high aspect ratio features into alternating SiO 2 and SiN layers is an enabling technology for the manufacturing of 3D NAND flash memories. In this paper, we study a low-temperature or cryo plasma etch process, which utilizes HF gas together with other gas additives. Compared with a low-temperature process that uses separate fluorine and hydrogen gases, the etching rate of the SiO 2 /SiN stack doubles. Both materials etch faster with this so-called second generation cryo etch process. Pure HF plasma enhances the SiN etching rate, while SiO 2 requires an additional fluorine source such as PF 3 to etch meaningfully. Further, the insertion of H 2 O plasma steps into the second generation cryo etch process boosts the SiN etching rate by a factor of 2.4, while SiO 2 etches only 1.3 times faster. We observe a rate enhancing effect of H 2 O coadsorption in thermal etching experiments of SiN with HF. Ammonium fluorosilicate (AFS) plays a salient role in etching of SiN with HF with and without plasma. AFS appears weakened in the presence of H 2 O. Density functional theory calculations confirm the reduction of the bonding energy when NH 4 F in AFS is replaced by H 2 O.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2025

Water-In-Glass: A Self-Supporting Inorganic Aqueous Electrolyte

Aqueous rechargeable sodium-ion batteries (ARNIBs) are emerging as cost-effective and safe candidates for large-scale energy storage applications. However, their advancement has been constrained by the narrow electrochemical stability window (ESW) of conventional aqueous electrolytes (1.23 V). Here, in this study, we present a transformative approach using an inexpensive and rapidly dissolvable inorganic glass material, water glass (W-glass), to significantly enhance the ESW and enable the development of solid-state, self-supporting aqueous film (SSA film) electrolytes. These SSA film electrolytes exhibit an extended ESW of up to 3.5 V and a conductivity of ∼10 –4 S/cm at room temperature. Structural analysis using magic-angle spinning nuclear magnetic resonance (NMR) and solution-state NMR reveals that the dissolution of W-glass in water is driven by the interdependent hydrolysis of P–O–P linkages and Na + –H + ion exchange. This work offers a cost-effective and scalable solution for advancing high-performance ARNIB technology, addressing critical barriers to commercial adoption.

Electrochemical stability window↗