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All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Passive Neutron Instrumentation and Applications

This chapter presents a description of most of the instruments that are currently in use for the measurement of plutonium and uranium using passive methods (without an external source). This includes the acquisition electronics as well as Singles counting methods, coincidence counting methods and multiplicity counting methods. The Singles counting applications include the measurement of waste and curium bearing materials. The coincidence counting applications include bulk plutonium, bulk uranium, waste and holdup measurements and fresh fuel assemblies. The multiplicity application description includes advantages and disadvantages and multiplicity detector design. There is also a description of some non-3He systems. The chapter concludes with a description of additional concepts: neutron imagers, list-mode data analysis, distributed source term analysis, unattended monitoring and MCNP modeling for detector design.

Coincidence shift register↗
DOE OSTI2022

Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

Here this paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6 μW and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.

42 ENGINEERING↗
DOE OSTI2023

Demonstration of INCC6 for advanced list-mode data acquisition and analysis using ALMM

The International Neutron Coincidence Counting (INCC) software plays an important role in nuclear safeguards and nuclear material control and accounting (NMC&A) measurements. While the current version, INCC5, represents the traditional standard utilized by inspectorates as well as facilities and practitioners alongside shift register hardware, LANL has recently developed an upgraded version of the software, INCC6. INCC6 offers the same analysis tools as INCC5 while adding new capabilities including acquisition and analysis of list-mode data, recording and storage of list-mode data files, and an expanded set of advanced analysis tools that make use of the additional information available from list-mode data. Here, this paper presents the first demonstration of data acquisition and analysis using INCC6 and the Advanced List Mode Multiplicity Module (ALMM). The capability of INCC6 to perform live list-mode data acquisition and analysis is demonstrated for a variety of neutron sources with a range of neutron emission rates relevant for practical applications and validated against the results obtained with INCC5 and traditional shift register hardware. Advanced list-mode analysis tools introduced by INCC6, such as time-interval and coincidence matrix analysis, are also demonstrated. Finally, the capability of INCC6 to analyze list-mode data files is tested and validated against traditional shift register results using INCC5.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Design of an 8-channel 40 GS/s 20 mW/Ch waveform sampling ASIC in 65 nm CMOS

One picosecond timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in TSMC 65 nm process targetting one picosecond resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing for picosecond time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC. PSEC5 has been submitted for fabrication.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Delay-locked-loop timing error mitigation

Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.

Filippini, Leo↗
DOE OSTI2023

Contact-Less Integrity Verification of Microelectronics Using Near-Field EM Analysis

Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics stems from piracy of intellectual properties (IP) and counterfeiting, which causes significant revenue loss to the semiconductor manufacturers. Further, these components often lead to compromised functionality, reliability, security, and safety of an electronic system. This paper presents secure information transmission and probing methods for verifying the integrity of digital integrated circuit (ICs) based on their electromagnetic (EM) near-field emissions and thereby protecting systems against counterfeit components. The proposed method has been tested on both high-level instructions executed by microprocessors or Systems-on-Chip (serving as examples of software), and also logic circuits within FPGA fabrics and ASICs (serving as examples of hardware). The authentication information required by each digital system is generated using a pseudo-random number generator circuit and securely transmitted via near-field magnetic emissions. The authorized party can probe these emissions using a near-field probe, process the acquired signals to improve the signal-to-noise ratio (SNR), and then recover the secure information through matched filtering. Experimental results from commercial SoCs are used to demonstrate the proposed technique. Methods for reducing EM interference during integrity verification of both FPGAs and ASICs are also described.

47 OTHER INSTRUMENTATION↗