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Parallelled charge transfer channels have multiple-phase-clocked gate electrodes overspanning them in one of a number of arrangements conditioning the transfer of charge packets in opposing directions in adjacent charge transfer channels. Three-phase, four-phase, five-phase and six-phase clocking arrangements constructed in three layers of polysilicon embody the invention.
The most important properties of shift register generated sequences are exposed. The application of shift registers as multiplication and division circuits leads to the generation of some error correcting and detecting codes.
This chapter presents a description of most of the instruments that are currently in use for the measurement of plutonium and uranium using passive methods (without an external source). This includes the acquisition electronics as well as Singles counting methods, coincidence counting methods and multiplicity counting methods. The Singles counting applications include the measurement of waste and curium bearing materials. The coincidence counting applications include bulk plutonium, bulk uranium, waste and holdup measurements and fresh fuel assemblies. The multiplicity application description includes advantages and disadvantages and multiplicity detector design. There is also a description of some non-3He systems. The chapter concludes with a description of additional concepts: neutron imagers, list-mode data analysis, distributed source term analysis, unattended monitoring and MCNP modeling for detector design.
Architecture developed for noise generator based on pseudorandom number sequence. Concept involves no additions or multiplications; outputs of set of feedback shift registers combined, bit-by-bit, in accordance with desired probability distribution. Digital, pseudorandom number output fed to digital-to-analog converter to generate pseudonoise signal suitable for testing broadband amplifiers.
A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other application-specific logic implementations on single integrated-circuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.
Here this paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6 μW and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.
Data processor with plural register stages for selectively interconnecting with each other to effect multiplicity of operations
The International Neutron Coincidence Counting (INCC) software plays an important role in nuclear safeguards and nuclear material control and accounting (NMC&A) measurements. While the current version, INCC5, represents the traditional standard utilized by inspectorates as well as facilities and practitioners alongside shift register hardware, LANL has recently developed an upgraded version of the software, INCC6. INCC6 offers the same analysis tools as INCC5 while adding new capabilities including acquisition and analysis of list-mode data, recording and storage of list-mode data files, and an expanded set of advanced analysis tools that make use of the additional information available from list-mode data. Here, this paper presents the first demonstration of data acquisition and analysis using INCC6 and the Advanced List Mode Multiplicity Module (ALMM). The capability of INCC6 to perform live list-mode data acquisition and analysis is demonstrated for a variety of neutron sources with a range of neutron emission rates relevant for practical applications and validated against the results obtained with INCC5 and traditional shift register hardware. Advanced list-mode analysis tools introduced by INCC6, such as time-interval and coincidence matrix analysis, are also demonstrated. Finally, the capability of INCC6 to analyze list-mode data files is tested and validated against traditional shift register results using INCC5.
Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).
Portable testing circuit enables technician to determine quickly wiring errors in multiple-conductor electrical cable or terminal connectors. Active unit tester made of inexpensive integrated circuits and other readily available components. Timer and one-shot generate pulses counted by shift registers. Shift-register output terminals wired to connector pins so voltage applied to each pin in sequence.
One picosecond timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in TSMC 65 nm process targetting one picosecond resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing for picosecond time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC. PSEC5 has been submitted for fabrication.
This paper describes the encoding and the decoding of a (31,15) Reed-Solomon Code for multiple-burst error correction for large memory systems. The decoding procedure consists of four steps: (1) syndrome calculation, (2) error-location polynomial calculation, (3) error-location numbers calculation, and (4) error values calculation. The principal features of the design are the use of a hardware shift register for both high-speed encoding and syndrome calculation, and the use of a commercially available (31,15) decoder for decoding Steps 2, 3 and 4.
Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.
The latitudinal behavior of intensities and multiplicities was registered by the neutron monitor 2 NM and the lead-free neutron monitor 3 SND (slow-neuron detector) in the equator-Kaliningrad line in the Atlantic Ocean. Coupling coefficients for 3 SND show the sensitivity of this detector to primary particles of cosmic rays of energies on the average lower than for 2 NM. As multiplicities increase, the coupling coefficients shift towards higher energies.
A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.
Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics stems from piracy of intellectual properties (IP) and counterfeiting, which causes significant revenue loss to the semiconductor manufacturers. Further, these components often lead to compromised functionality, reliability, security, and safety of an electronic system. This paper presents secure information transmission and probing methods for verifying the integrity of digital integrated circuit (ICs) based on their electromagnetic (EM) near-field emissions and thereby protecting systems against counterfeit components. The proposed method has been tested on both high-level instructions executed by microprocessors or Systems-on-Chip (serving as examples of software), and also logic circuits within FPGA fabrics and ASICs (serving as examples of hardware). The authentication information required by each digital system is generated using a pseudo-random number generator circuit and securely transmitted via near-field magnetic emissions. The authorized party can probe these emissions using a near-field probe, process the acquired signals to improve the signal-to-noise ratio (SNR), and then recover the secure information through matched filtering. Experimental results from commercial SoCs are used to demonstrate the proposed technique. Methods for reducing EM interference during integrity verification of both FPGAs and ASICs are also described.
Long duration spaceflight (i.e., 22 days or longer) has been associated with changes in sensorimotor systems, resulting in difficulties that astronauts experience with posture control, locomotion, and manual control. The microgravity environment is an important causal factor for spaceflight induced sensorimotor changes. Whether these sensorimotor changes are solely related to peripheral changes from reduced vestibular stimulation, body unloading, body fluid shifts or that they may be related to structural and functional brain changes is yet unknown. However, a recent study reported associations between microgravity and flattening of the posterior eye globe and protrusion of the optic nerve [1] possibly as the result of increased intracranial pressure due to microgravity induced bodily fluid shifts [3]. Moreover, elevated intracranial pressure has been related to white matter microstructural damage [2]. Thus, it is possible that spaceflight may affect brain structure and thereby cognitive functioning. Long duration head down tilt bed rest has been suggested as an exclusionary analog to study microgravity effects on the sensorimotor system [4]. Bed rest mimics microgravity in body unloading and bodily fluid shifts. In consideration of the health and performance of crewmembers both in- and post-flight, we are conducting a prospective longitudinal 70-day bed rest study as an analog to investigate the effects of microgravity on brain structure [5]. Here we present results of the first six subjects. Six subjects were assessed at 12 and 7 days before-, at 7, 30, and ~70 days in-, and at 8 and 12 days post 70 days of bed rest at the NASA bed rest facility in UTMB, Galveston, TX, USA. At each time point structural MRI scans (i.e., high resolution T1-weighted imaging and Diffusion Tensor Imaging (DTI)) were obtained using a 3T Siemens scanner. Focal changes over time in gray matter density were assessed using the voxel based morphometry 8 (VBM8) toolbox under SPM. Longitudinal processing in VBM8 includes linear registration of each scan to the mean of the subject and subsequently transforming all scans in to MNI space by applying the warp from the mean subject to MNI to the individual gray matter segmentations. Modulation was applied so that all images represented the volume of the original structure in native space. Voxel wise analysis was carried out on the gray matter images after smoothing, using a flexible factorial design with family wise error correction. Focal changes in white matter microstructural integrity were assessed using tract based spatial statistics (TBSS) as part of FMRIB software library (FSL). TBSS registers all DTI scans to standard space. It subsequently creates a study specific white matter skeleton of the major white matter tracts. For each subject, for each DTI metric (i.e. fractional anisotropy (FA), mean diffusivity (MD), axial diffusivity (AD), and radial diffusivity (RD)), the maximum value in a line perpendicular to the skeleton tract is projected to the skeleton. Non-parametric permutation based t-tests and ANOVA's were used for voxel-wise comparison of the skeletons. For both VBM and TBSS, comparison of pre bed rest measurements did not show significant differences. VBM analysis revealed decreased gray matter density in bilateral areas including the frontal medial cortex, the insular cortex and the caudate (see Figure) from 'pre to in bed rest'. Over the same time period, there was an increase in gray matter density in the cerebellum, occipital-, and parietal cortex, including the precuneus (see Figure). The majority of these changes did not recover from 'during to post bed rest'. TBSS analysis did not reveal significant changes in white matter microstructural integrity after correction for multiple comparisons. Uncorrected analyses (p<.015) revealed an increase in RD in the cerebellum and brainstem from pre bed rest to the first week in bed rest that did not recover post bed rest. Extended bed rest, which is an analog for microgravity, can result in gray matter changes and potentially in microstructural white matter changes in areas that are important for neuro motor behavior and cognition. These changes did not recover at two weeks post bed rest. Whether the effects of bed rest wear off at longer times post bed rest, and if they are associated with behavior are important questions that warrant further research.