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Advanced packaging technologies such as 3D chip stacking, multichip modules (MCMs), and 3D stacks of MCMs provide opportunities for significant reductions in system mass, volume and power.
A Multichip Module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's new 'cheaper, faster, better' missions.
This paper summarizes and reports a radiation hardened Spacecraft Integrated Circuit Technology to be flown on board the Cassini spacecraft in 1997 A.D. The Multichip Module has been designed to have an operating life of fifeteen (15) years with appropriate derating guidelines for high reliability.
NASA Goddard Space Flight Center has designed a high-density modular 3-D multichip module (MCM) for future spaceflight use. This MCM features a complete modular structure, i.e., each stack can be removed from the package without damaging the structure. The interconnection to the PCB is through the Column Grid Array (CGA) technology. Because of its high-density nature, large power dissipation from multiple layers of circuitry is anticipated and CVD diamond films are used in the assembly for heat conduction enhancement. Since each stacked layer dissipates certain amount of heat, designing effective heat conduction paths through each stack and balancing the heat dissipation within each stack for optimal thermal performance become a challenging task. To effectively remove the dissipated heat from the package, extensive thermal analysis has been performed with finite element methods. Through these analyses, we are able to improve the thermal design and increase the total wattage of the package for maximum electrical performance. This paper provides details on the design-oriented thermal analysis and performance enhancement. It also addresses issues relating to contact thermal resistance between the diamond film and the metallic heat conduction paths.
Recent changes within NASA's space exploration program favor the design, implementation, and operation of low cost, lightweight, small and micro spacecraft with multiple launches per year. In order to meet the future needs of these missions with regard to the use of spacecraft microelectronics, NASA's advanced flight computing (AFC) program is currently considering industrial cooperation and advanced packaging architectures. In relation to this, the AFC program is reviewed, considering the design and implementation of NASA's AFC multichip module.
This paper summarizes and reports a radiation hardened Spacecraft Integrated Sensor/Circut Technology that has been delivered for flight applications to be flown on board STRV-2 (Space Technology Research Vehicle-2).
Various stripline structures and flip chip interconnect designs for high-speed digital communication systems implemented in low temperature co-fired ceramic (LTCC) substrates are studied in this paper. Specifically, two different transition designs from edge launch 2.4 millimeter connectors to stripline transmission lines embedded in LTCC are discussed. After characterizing the DuPont (sup trademark) 9K7 green tape, different designs are proposed to improve signal integrity for high-speed digital data. The full-wave simulations and experimental data validate the presented designs over a broad frequency band from Direct Current to 50 gigahertz and beyond.
A device has been developed for coherent detection of the polarization of the cosmic microwave background (CMB). A two-stage amplifier has been designed that covers 75-110 GHz. The device uses the emerging 35-nm InP HEMT technology recently developed at Northrop Grumman Corporation primarily for use at higher frequencies. The amplifier has more than 18 dB gain and less than 35 K noise figure across the band. These devices have noise less than 30 K at 100 GHz. The development started with design activities at JPL, as well as characterization of multichip modules using existing InP. Following processing, a test campaign was carried out using single-chip modules at 100 GHz. Successful development of the chips will lead to development of multichip modules, with simultaneous Q and U Stokes parameter detection. This MMIC (monolithic microwave integrated circuit) amplifier takes advantage of performance improvements intended for higher frequencies, but in this innovation are applied at 90 GHz. The large amount of available gain ultimately leads to lower possible noise performance at 90 GHz.
This paper describes a working flight computer Multichip Module developed jointly by JPL and TRW under their respective research programs in a collaborative fashion. The MCM is fabricated by nCHIP and is packaged within a 2 by 4 inch Al package from Coors. This flight computer module is one of three modules under development by NASA's Advanced Flight Computer (AFC) program. Further development of the Mass Memory and the programmable I/O MCM modules will follow. The three building block modules will then be stacked into a 3D MCM configuration. The mass and volume of the flight computer MCM achieved at 89 grams and 1.5 cubic inches respectively, represent a major enabling technology for future deep space as well as commercial remote sensing applications.
The intent of this presentation is to give a brief look into the future of electronic packaging for microspacecraft applications. Advancements in electronic packaging technology areas have developed to the point where a system engineer's visions, concepts, and requirements for a microspacecraft can now be a reality. These new developments are ideal candidates for microspacecraft applications. These technologies are capable of bringing about major changes in how we design future spacecraft while taking advantage of the benefits due to size, weight, power, performance, reliability , and cost. This presentation will also cover some advantages and limitations of surface mount technology (SMT), multichip modules (MCM), and wafer scale integration (WSI), and what is needed to implement these technologies into microspacecraft.
To meet new design objectives for drastic reductions in mass, size, and power consumption, the Flight Computer Development Group at JPL is participating in a design study and development of a light-weight, small-sized, low-power 3-D Space Flight Computer. In this paper, we will present a detailed design and tradeoff study of the proposed computer. We will also discuss a complete design of the multichip modules and their size, weight, and power consumption. Prelimimary thermal models will also be discussed.
A flexible computer architecture based on stacked interchangeable modules is ideally suited to implementation using stacked multichip modules. Its use of all sides of a module stack allows simple, single-bussed modules, together with a gateway module, to be easily configured into a variety of more complicated architectures.
The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.
We have developed and demonstrated miniature 180 GHz Monolithic Microwave Integrated Circuit (MMIC) radiometer modules that have low noise temperature, low mass and low power consumption. These modules will enable the Geostationary Synthetic Thinned Aperture Radiometer (GeoSTAR) of the Precipitation and All-weather Temperature and Humidity (PATH) Mission for atmospheric temperature and humidity profiling. The GeoSTAR instrument has an array of hundreds of receivers. Technology that was developed included Indium Phosphide (InP) MMIC Low Noise Amplifiers (LNAs) and second harmonic MMIC mixers and I-Q mixers, surface mount Multi-Chip Module (MCM) packages at 180 GHz, and interferometric array at 180 GHz. A complete MMIC chip set for the 180 GHz receiver modules (LNAs and I-Q Second harmonic mixer) was developed. The MMIC LNAs had more than 50% lower noise temperature (NT=300K) than previous state-of-art and MMIC I-Q mixers demonstrated low LO power (3 dBm). Two lots of MMIC wafers were processed with very high DC transconductance of up to 2800 mS/mm for the 35 nm gate length devices. Based on these MMICs a 180 GHz Multichip Module was developed that had a factor of 100 lower mass/volume (16x18x4.5 mm3, 3g) than previous generation 180 GHz receivers.
A 180-GHz interferometric imager uses compact receiver modules, combined high- and low-gain antennas, and ASIC (application specific integrated circuit) correlator technology, enabling continuous, all-weather observations of water vapor with 25-km resolution and 0.3-K noise in 15 minutes of observation for numerical weather forecasting and tropical storm prediction. The GeoSTAR-II prototype instrument is broken down into four major subsystems: the compact, low-noise receivers; sub-array modules; IF signal distribution; and the digitizer/correlator. Instead of the single row of antennas adopted in GeoSTAR, this version has four rows of antennas on a coarser grid. This dramatically improves the sensitivity in the desired field of view. The GeoSTAR-II instrument is a 48-element, synthetic, thinned aperture radiometer operating at 165-183 GHz. The instrument has compact receivers integrated into tiles of 16 elements in a 4x4 arrangement. These tiles become the building block of larger arrays. The tiles contain signal distribution for bias controls, IF signal, and local oscillator signals. The IF signals are digitized and correlated using an ASIC correlator to minimize power consumption. Previous synthetic aperture imagers have used comparatively large multichip modules, whereas this approach uses chip-scale modules mounted on circuit boards, which are in turn mounted on the distribution manifolds. This minimizes the number of connectors and reduces system mass. The use of ASIC technology in the digitizers and correlators leads to a power reduction close to an order of magnitude.
The next generation of experiments for light-dark-matter and neutrino searches based on skipper charge-coupled devices (skipper-CCDs) introduces new challenges for the sensor packaging and readout architecture. Scaling the active mass while simultaneously reducing the experimental backgrounds in orders of magnitude requires a novel high-density silicon-based package that must be massively produced and tested. In this work, we present a silicon multichip module design capable of hosting up to 16 skipper-CCDs, along with the fabrication process for the first prototypes. We thoroughly tested and characterized the assembled prototypes to build an empirical model for the video output signal of skipper-CCDs integrated into the silicon package. We then used this model in simulations to optimize the fabrication process and achieve the robust performance required for the full-scale array, which we validated through a new round of prototype fabrication. We outline the specifications selected for the ongoing production of 1500 silicon wafers that will ultimately add up to a 10-kg skipper-CCD array with 24000 readout channels.
The processing and performance characteristics of a soluble, thermoplastic polyquinoline suggest its utility in a variety of high performance applications. The polymer is characterized by excellent thermal and oxidative stability, very low moisture absorption, good mechanical properties, very low dielectric constant, and an unusually low thermal expansion coefficient. This polymer, designated PQ-100 (TM), can be cast into strong, transparent, free standing films from common solvents. Coatings of variable thickness can be spin-coated on to silicon and other surfaces. After processing into films, PQ-100 (TM) can be rendered insoluble in a wide range of solvents using a proprietary process. The low CTE contributes to very low residual stress when the polymer is spin-coated onto silicon wafers. PQ-100 (TM) is currently under evaluation for use as an interlayer dielectric substrate in high-density interconnect applications, including multichip modules. Many of the characteristics of the polymer also suggest its utility as a high-performance film and as a matrix resin for specialty composite applications.
A joint military-commercial effort to evaluate multichip module (MCM) structures is discussed. The program, Reliability Technology to Achieve Insertion of Advanced Packaging (RELTECH), has been designed to identify the failure mechanisms that are possible in MCM structures. The RELTECH test vehicles, technical assessment task, product evaluation plan, reliability modeling task, accelerated and environmental testing, and post-test physical analysis and failure analysis are described. The information obtained through RELTECH can be used to address standardization issues, through development of cost effective qualification and appropriate screening criteria, for inclusion into a commercial specification and the MIL-H-38534 general specification for hybrid microcircuits.