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An Inclusive Structural Analysis on the Design of 1.2kV 4H-SiC Planar MOSFETs
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A Comparison of Radiation-Induced and High-Field Electrically Stress-Induced Interface Defects in Si/SiO 2 MOSFETs via Electrically Detected Magnetic Resonance
Here, we utilize electrically detected magnetic resonance (EDMR) measurements to compare high-field stressed, and gamma irradiated Si/SiO 2 metal–oxide–silicon (MOS) structures. We utilize spin-dependent recombination (SDR) EDMR detected using the Fitzgerald and Grove dc I-V approach to compare the effects of high-field electrical stressing and gamma irradiation on defect formation at and near the Si/SiO 2 interface. As anticipated, both greatly increase the concentration of P b centers (silicon dangling bonds at the interface) densities. The irradiation also generated a significant increase in the dc I-V EDMR response of E' centers (oxygen vacancies in the SiO 2 films), whereas the generation of an E' EDMR response in high-field stressing is much weaker than in the gamma irradiation case. These results likely suggest a difference in their physical distribution resulting from radiation damage and high electric field stressing.
A New Class of SiC Power MOSFETs with Record-Low Resistance
Silicon carbide (SiC) power transistors are used in the main traction inverter of electric vehicles (EVs). Tesla began installing SiC power MOSFETs in 2017, and has now produced 4.8 million EVs containing over 169 million SiC power MOSFETs. Looking ahead, the worldwide EV market is projected to exceed 50 million vehicles per year by 2030 (Reuters, Oct. 25, 2022). This will create a demand for over two billion SiC power MOSFETs per year. Our program aims to double the efficiency of today's commercial power MOSFETs. This will cut the number of MOSFETs per EV in half, reducing cost, simplifying assembly, decreasing weight, and increasing vehicle reliability through reduced parts count. Our approach is to apply innovative design and advanced processing to increase the density of current-controlling channels in SiC power MOSFET. We have developed two new MOSFET devices, each of which increases the channel density by a factor of six over today's best commercial MOSFETs. This required implementing new fabrication processes, creating new device designs, and integrating the processing steps and device designs into a manufacturable technology. In this project we have developed two innovative devices: (i) a novel three-dimensional structure, the "tri-gate MOSFET," and (ii) a deeply-scaled, fully self-aligned trench MOSFET, the "IMOSFET". Both products were experimentally demonstrated during this project and meet the program goals of increased efficiency relative to the current state-of-the art commercial products. In the process we have generated significant IP, with two US patents issued and three applications pending. We have also published three journal articles and given reports on this technology at seven international conferences. The success of this program has led to significant follow-on funding from industry. In May 2023 Purdue University signed a five-year R&D contract with GlobalFoundries to transfer our novel technology to commercial production. With headquarters in Malta, NY, Global Foundries is one of the largest pure-play silicon foundries in the world, with annual revenue of $\$$8.1B. Their SiC foundry will be built around the next-generation 200-mm diameter SiC wafers, which will double the number of die per wafer and reduce per-die production cost.
Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs
This paper evaluates the impact of the fast high gate-voltage screening technique on gate oxide reliability of commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The measurements are conducted on packaged devices with the intent that the results will be applicable to wafer-level screening. The threshold voltage (V th ) of SiC MOSFETs is measured before and after various screening treatments and recovery process. In addition, constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on SiC MOSFETs to obtain the intrinsic lifetime of gate oxide. The objective of this study is to determine the optimal screening conditions and improve screening efficiency without degradation of gate oxide reliability, such as V th shift and reduced oxide intrinsic lifetime. Due to the differences in the gate oxidation process and structural design of SiC planar and trench MOSFETs, the two types of devices exhibit different oxide reliability in the screening process. The recommended screening conditions obtained in this paper reveal that SiC trench MOSFETs can accept higher screening voltages compared to SiC planar MOSFETs. Hence, it can be concluded that more efficient screening techniques can be adopted for SiC MOSFETs with thicker gate oxide to meet the requirements of industrial applications.
Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis
The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field (E eƒƒ ) on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be E$^{-1.8}_{eƒƒ}$ and E$^{-2.4}_{eƒƒ}$, respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of E eƒƒ in controlling the value of channel mobility in 4H-SiC MOSFETs.
Feasibility of Passive MOSFET Paralleling for Photovoltaic Current-Voltage Curves
Current-voltage curves are an important method of characterizing Photovoltaic (PV) Modules. NREL has developed several low-cost MOSFET-based devices that can characterize PV cells and modules. The size of PV modules that can be measured is limited by the power limitations of a single MOSFET. By using multiple MOSFET devices, each can operate at a lower current, paralleled on resistance is also decreased allowing for higher power loads. Operating multiple devices in parallel can cause an imbalance in current, thus causing some devices to conduct more, pushing them into a thermal runaway condition. To investigate this, an active feedback circuit was tested with paralleled devices using a PV module load. The efficacy, limitations, and design considerations of using parallel MOSFET loads for PV characterization are explored. This work is not new, but the implementation of a paralleled architecture in a low cost characterization tool is novel.
Comparison and Discussion on Shortcircuit Protections for Silicon-Carbide MOSFET Modules: Desaturation Versus Rogowski Switch-Current Sensor
Survivability of silicon-carbide (SiC) mosfet modules during short circuit (SC) is essential for modern power electronics systems due to large economic implications. SiC mosfet modules exhibit narrow SC withstand times and generally much lower SC robustness than silicon (Si) insulated-gate bipolar transistors (IGBTs). This puts a critical concern on their utilization, further stressing the importance of reliable protection. This article presents a comprehensive analysis and discussion on the SiC mosfet module SC protection and performance comparison between conventional desaturation detection, previously used for Si IGBT protection, and Rogowski switch-current sensor (RSCS) detection. In addition, this article presents the experimental design for soft turn-off as a reaction to the SC detection to avoid excessive overshoots during the abrupt turn-off of the SC current. To perform different types of SC with various fault inductances on different temperatures, and for the sake of fair comparison under the same conditions, a gate-driver unit for 1.2 kV SiC mosfet half-bridge modules is developed containing both detection methods. The results demonstrate that both methods are successful in protecting the module in all SC types, with superiority of the RSCS detection and concerns for desaturation detection in high-inductance and high dc-bus voltage SC events.
A High-Accuracy Power Loss Model of SiC MOSFETs in Current Source Inverter Considering Current Commutation and Parasitic Parameters
Power loss estimation of power electronic devices is important to the efficiency optimization of motor drives used in many applications. However, most existing simplified power loss models of silicon carbide (SiC) MOSFETs are not sufficiently accurate due to their neglect of parasitic parameters in the current commutation loop. In addition, the loss model of the voltage source inverter (VSI) cannot be directly applied to the current source inverter (CSI) because of differences between their commutation loops. First, the commutation processes for VSIs and CSIs are compared. The voltage and current trajectories of SiC MOSFETs in the switching transition of a CSI-based motor drive system are analyzed in detail. Based on these results, the conduction and switching losses of SiC MOSFETs in CSIs are modeled considering the current commutation details. In addition, the proposed analytical model includes parasitic inductances and capacitances in the current commutation loop. Experimental results have verified that the proposed power loss model delivers higher accuracy loss predictions than the conventional loss model.
A PCB-Embedded 1.2 kV SiC MOSFET Half-Bridge Package for a 22 kW AC–DC Converter
This article presents the design and analysis of a double-side-cooled printed circuit board (PCB) embedded silicon carbide (SiC) MOSFET half-bridge package with low loop inductances and an integrated gate driver. The 1.2 kV SiC MOSFET dies used in the half-bridge package are embedded in the PCB using AT&S's patented technique. The dies are cooled and electrically connected to traces in the PCB through copper-filled microvias. The design methodology accounts for both electrical and thermal performance, limiting the power-loop inductance to 2.3 nH and the maximum package temperature to less than the 175 °C limit. The integration of the gate drive circuitry allows for a high power density and 2.2 nH gate-loop inductances. At 0.12 K/W, the measured junction-to-case thermal resistance with double-sided cooling is 57% lower than that of a TO-247 package. Under similar operating conditions, the PCB-embedded half-bridge package also achieves a 5.6 times lower voltage overshoot and a 0.5% higher peak efficiency than a TO-247-based half-bridge. This article reports the first demonstration of PCB-embedded 1.2 kV SiC MOSFET packages in buck, boost, and ac–dc converters. Furthermore, the prototype three-phase ac–dc converter for an electric vehicle on-board charger is composed of six PCB-embedded half-bridge packages and achieves an efficiency of 98.2% and a power density of 182 W/in 3 .
A Comparison of Ion Implantation at Room Temperature and Heated Ion Implantation on the Body Diode Degradation of Commercial 3.3 kV 4H-SiC Power MOSFETs
It has been demonstrated that basal plane dislocations (BPDs)-induced stacking faults (SFs) cause body diode degradation in commercial 4H-SiC power MOSFETs, especially with higher voltage ratings. BPDs originate from 4H-SiC boule, epi growth, and ion implantation. Considering the lower cost of ion implantation at room temperature (RT), this work investigates the potential of RT ion implantation replacing heated (HT) ion implantation by comparing the influence of both ion implantations on the body diode degradation of commercial 3.3 kV 4H-SiC power MOSFETs. We demonstrate with long-term (up to 1000 hours) forward current stress that RT implantation can keep the body diode degradation of 3.3 kV 4H-SiC power MOSFETs within the specification limits compared with HT implantation.
Investigation of the Effect of Gate Oxide Screening with Adjustment Pulse on Commercial SiC Power MOSFETs
This paper presents a method to recover the negative threshold voltage shift during high field gate oxide screening of 1.2 kV 4H-SiC MOSFETs with an additional adjustment gate voltage pulse. To reduce field failure rates of the MOSFETs in operation, manufacturers perform a screening treatment to remove devices with extrinsic defects in the oxide. Current gate oxide screening procedures are limited to oxide fields at or below ~9 MV/cm for short durations (<1 s), which is not enough to remove all the devices with extrinsic defects. The results show that by implementing a lower field gate pulse, the threshold voltage shift can be partially recovered, and therefore the maximum screening field and time can be increased. However, both the initial screening pulse and the adjustment pulse require careful calibration to prevent significant degradation of the device threshold voltage, on-resistance, interface state density, or intrinsic lifetime. With a well calibrated set of pulses, higher screening fields can be utilized without significantly damaging the devices. This leads to an improvement in the overall screening efficiency of the process, reducing the number of devices with extrinsic oxide defects entering the field, and improving the reliability of the SiC MOSFETs in operation.
Achieving Single-Electron Sensitivity at Enhanced Speed in Fully-Depleted CCDs with Double-Gate MOSFETs
We introduce a new output amplifier for fully-depleted thick p-channel CCDs based on double-gate MOSFETs. The charge amplifier is an n-type MOSFET specifically designed and operated to couple the fully-depleted CCD with high charge-transfer efficiency. The junction coupling between the CCD and MOSFET channels has enabled high sensitivity, demonstrating sub-electron readout noise in one pixel charge measurement. We have also demonstrated the non-destructive readout capability of the device. Achieving single-electron and single-photon per pixel counting in the entire CCD pixel array has been made possible through the averaging of a small number of samples. We have demonstrated fully-depleted CCD readout with better performance than the floating diffusion and floating gate amplifiers available today, in both single and multisampling regimes, boasting at least six times the speed of floating gate amplifiers.
Radiation Response of Ga 2 O 3 MOSFETs Probed via Focused Particle Beams
Gallium Oxide (Ga 2 O 3 ), particularly in its β-phase, is attracting lots of interest for high-power and high-voltage electronics due to its wide bandgap, high breakdown field, and thermal stability. This study investigates the radiation response of Ga 2 O 3 Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) under Total Ionizing Dose (TID) and Displacement Damage (DD) conditions, which are critical for applications in radiation environments. Utilizing a dual-beam Focused Ion Beam and Scanning Electron Microscope setup, microscale analysis of radiation effects on individual devices is performed. The findings reveal distinct behaviors under TID and DD + TID conditions, with TID leading to threshold voltage shifts due to trapped charges, while DD results in decreased drive current attributed to increased carrier scattering from lattice defects. Notably, it is demonstrated that the TID effect can be mitigated through dynamic threshold voltage adjustments and that the predicted TID from ions calculated by Monte Carlo simulations overestimates actual TID due to unaccounted charge yield effects. In conclusion, this research enhances the understanding of Ga2O3 MOSFETs' performance in harsh radiation environments, providing insights for the design of robust electronic devices for space and nuclear applications.
A Study of Integrated Signal and Power Transfer for Compact Isolated SiC MOSFET Gate-Drivers
This work discusses a novel set of alternate implementations of isolated gate driver circuits for power electronic transistors. The proposed topologies for the driver have been designed specifically for SiC power MOSFET. Three different solutions are discussed, all of them providing the required gate turn-on and turn-off command signal with galvanic isolation, but also supplying power to the secondary side of the driver by means of magnetic transformers. The resulting solutions, all of them implemented with simple circuitry, enable the integration of the driver into the power cell, allowing for theoretical higher power density values in the final system. The principle of operation of the different solutions is discussed, and then the main relevant implementation details are presented. After that, the operation of the circuits is demonstrated experimentally, by testing a set of prototypes of these drivers. This provides a comprehensive design example that assesses the feasibility of the proposed solutions. Finally, the main results of the performance of the three gate drivers, on an SiC MOSFET-based prototype are presented and compared.
A trapping tolerant drain current based temperature measurement of β -Ga 2 O 3 MOSFETs
The drain current temperature dependence is an efficient way to determine the channel temperature in semiconductor devices; however, it has been challenging to use due to the potential interference of trapping effects. A trapping tolerant method is proposed, illustrated here for Ga 2 O 3 MOSFETs, making in situ temperature measurements possible, allowing a thermal resistance of 59 K∙mm/W to be measured in Ga 2 O 3 MOSFETs. However, neglecting the effect of trapping causes an error of ~15% in the channel temperature measured using the drain current. 3D simulations show that the measured channel temperature is the average temperature value between source and drain contact.