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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Feasibility of Passive MOSFET Paralleling for Photovoltaic Current-Voltage Curves

Current-voltage curves are an important method of characterizing Photovoltaic (PV) Modules. NREL has developed several low-cost MOSFET-based devices that can characterize PV cells and modules. The size of PV modules that can be measured is limited by the power limitations of a single MOSFET. By using multiple MOSFET devices, each can operate at a lower current, paralleled on resistance is also decreased allowing for higher power loads. Operating multiple devices in parallel can cause an imbalance in current, thus causing some devices to conduct more, pushing them into a thermal runaway condition. To investigate this, an active feedback circuit was tested with paralleled devices using a PV module load. The efficacy, limitations, and design considerations of using parallel MOSFET loads for PV characterization are explored. This work is not new, but the implementation of a paralleled architecture in a low cost characterization tool is novel.

14 SOLAR ENERGY↗
DOE OSTI2025

Investigation of the Effect of Gate Oxide Screening with Adjustment Pulse on Commercial SiC Power MOSFETs

This paper presents a method to recover the negative threshold voltage shift during high field gate oxide screening of 1.2 kV 4H-SiC MOSFETs with an additional adjustment gate voltage pulse. To reduce field failure rates of the MOSFETs in operation, manufacturers perform a screening treatment to remove devices with extrinsic defects in the oxide. Current gate oxide screening procedures are limited to oxide fields at or below ~9 MV/cm for short durations (<1 s), which is not enough to remove all the devices with extrinsic defects. The results show that by implementing a lower field gate pulse, the threshold voltage shift can be partially recovered, and therefore the maximum screening field and time can be increased. However, both the initial screening pulse and the adjustment pulse require careful calibration to prevent significant degradation of the device threshold voltage, on-resistance, interface state density, or intrinsic lifetime. With a well calibrated set of pulses, higher screening fields can be utilized without significantly damaging the devices. This leads to an improvement in the overall screening efficiency of the process, reducing the number of devices with extrinsic oxide defects entering the field, and improving the reliability of the SiC MOSFETs in operation.

42 ENGINEERING↗
DOE OSTI2025

Radiation Response of Ga 2 O 3 MOSFETs Probed via Focused Particle Beams

Gallium Oxide (Ga 2 O 3 ), particularly in its β-phase, is attracting lots of interest for high-power and high-voltage electronics due to its wide bandgap, high breakdown field, and thermal stability. This study investigates the radiation response of Ga 2 O 3 Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) under Total Ionizing Dose (TID) and Displacement Damage (DD) conditions, which are critical for applications in radiation environments. Utilizing a dual-beam Focused Ion Beam and Scanning Electron Microscope setup, microscale analysis of radiation effects on individual devices is performed. The findings reveal distinct behaviors under TID and DD + TID conditions, with TID leading to threshold voltage shifts due to trapped charges, while DD results in decreased drive current attributed to increased carrier scattering from lattice defects. Notably, it is demonstrated that the TID effect can be mitigated through dynamic threshold voltage adjustments and that the predicted TID from ions calculated by Monte Carlo simulations overestimates actual TID due to unaccounted charge yield effects. In conclusion, this research enhances the understanding of Ga2O3 MOSFETs' performance in harsh radiation environments, providing insights for the design of robust electronic devices for space and nuclear applications.

MOSFET↗
DOE OSTI2025

Off-state magnetoresistance in long-channel germanium Schottky-barrier MOSFETs

An increasing magnetic field perpendicular to an undoped semiconductor surface at low temperature is known to strengthen the binding of localized electrons to stationary ions, as the wavefunction's tails evolve from exponential to Gaussian. It is also known that application of a high bias voltage to a depleted semiconductor can liberate bound charge and induce a large drop in electrical resistance. We connect these established results to experimental electrical transport measurements on off-state germanium Schottky-barrier metal–oxide–semiconductor field-effect transistor (MOSFETs) with an aluminum oxide insulating dielectric and platinum germanide contacts. We make measurements at the three distinct orientations of the magnetic field with respect to the substrate and the current. At 6 K, we observe sharp attenuation of current by more than 2 orders of magnitude, within 60 mT, at a crossover magnetic field perpendicular to the substrate. A 1 T magnetic field attenuates the current by more than 4 orders of magnitude. The strength of the attenuation and the value of the crossover field are controlled by both the gate–source and drain–source voltages. The attenuation is much weaker when the magnetic field is parallel to the current. Finally, we orient the magnetic field parallel to the substrate, but perpendicular to the current, allowing us to distinguish charge hopping at the oxide interface from charge hopping in the bulk. In conclusion, this large off-state magnetoresistance can be exploited for cryogenic magnetic- and photo-detection, and for high-bias, low-leakage MOSFETs.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2025

Temperature-Agnostic Pt/Au Ohmic Contacts on n -Type Gallium Nitride for Self-Aligned MOSFETs

Five alternative metals are investigated as ohmic contacts to n-GaN including Cr/Au, Mo/Au, Pt/Au, Pd/Au, and Ge/Au. Ti-based contacts are traditionally used for ohmic contacts on n-GaN. However, conventional Ti/Al/Ni/Au metallization is found to be incompatible with a self-aligned process for GaN trench MOSFETs due to wet etch restrictions. Therefore, an alternative metallization is needed that is unreactive to the etch chemistry used in the self-aligned process. Additionally, the contact should remain ohmic following anneal at 900 °C so that contact formation can precede the anneal required for p-dopant activation. Here, in the present work, an n-GaN bilayer, consisting of a thin heavily doped contact layer (n 0 = 1 × 10 20 cm −3 ) atop a thick lesser doped layer, is used to demonstrate ohmic contacts of alternative metals with low specific contact resistance and extended thermal budget. Cr/Au ohmic contacts are demonstrated up to anneal temperatures of 800 °C, an increase of 200 °C compared to the highest known reports for Cr/Au contacts on n-GaN. Pt/Au metallization is demonstrated as an ohmic contact to n-GaN for the first time and exhibits true temperature-agnostic behavior up to anneal temperatures of 900 °C with specific contact resistance that is near parity with Ti/Al/Ni/Au. The temperature-agnostic behavior of Pt/Au ohmic contacts on the n-GaN bilayer, in addition to chemical compatibility with the self-aligned process, positions Pt/Au contacts as a key enabling element for self-aligned trench MOSFETs on GaN.

Reilly, Kevin James [Sandia National Laboratories ↗
DOE OSTI2026

TCAD-Machine Learning Enabled TID Compact Model Development for Commercial SiC MOSFET

We propose a TCAD (Technology Computer Aided Design)-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (V th ) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced V th shifts behavior with total doses and V th shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with few modifications and can provide well-determined uncertainties.

COTS↗
DOE OSTI2024

An Organic, Direct Bonded Copper, Multi-Layered, Ultra-Low Inductance Package for High-Power UWBG MOSFETs

The most common metalized substrates used in high-power switching packages consist of a ceramic layer such as Aluminum Nitride (AlN) sandwiched between two copper layers. Ceramic substrates are used because it has the key characteristic of having high dielectric strength while being thermally conductive. A large drawback to ceramic substrates is that they do not allow for a multi-layered circuit design. By replacing the traditional ceramic substrate with organic direct bonded copper (ODBC) we can open a wide range of possibilities when it comes to power module layout such as multi-layered circuits and double-sided cooling. Both benefits are critical while packaging high-performance Gallium Oxide (Ga2O3) MOSFETs. Because of Ga2O3's relatively poor thermal conductivity, a double-sided cooled package becomes necessary. Therefore, the use of ODBC provides the flexibility to fabricate copper traces carrying much higher currents, and by creating a multi-layered package, we can drastically reduce the parasitic inductance inside the power module. Achieving lower parasitic inductance is critical for an ultra-fast Ga2O3 package to avoid excessive voltage overshoot and ringing. Using ODBC, we have designed novel packages capable of handling the challenges presented by fast Ga2O3 switching. Using multi-physics modeling software, we can validate our design before building the prototype. Due to the simple process parameters needed to work with ODBC, we can rapidly create prototypes without using external vendors. This flexibility allows us to quickly design, build, and validate highly complex switching power modules to accommodate next generation, Ga2O3 switching devices.

ADVANCED PROPULSION SYSTEMS,ENGINEERING↗
DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗
DOE OSTI2026

DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77 K Using BSIM4

Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77 K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to operate at temperatures as low as 4 K making it a promising candidate for HEP applications. In this work, we characterize and model SKY130 low-threshold voltage transistors at 77 K, which is a temperature commonly used in modeling applications for liquid argon detectors. DC characteristic measurements were performed at both room temperature and liquid nitrogen temperature. We created a cryogenic modeling approach to produce a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77 K. The resulting model agrees with data at 77 K with an average error on the order of 20% (relative RMS) and shows no dependence on drain voltage. Due to the open-source nature of SKY130, we have made our models publicly available on Github. We hope this work will continue the trend for democratizing circuit design at cryogenic temperatures in high-energy physics by enabling open access to accurate cryogenic CMOS device models at 77 K.

Beall, F. [Texas U., Arlington]↗
DOE OSTI2024

Quench protection for high-temperature superconductor cables using active control of current distribution

Superconducting magnets of future fusion reactors are expected to rely on composite high-temperature superconductor (HTS) cable conductors. In presently used HTS cables, current sharing between components is limited due to poorly defined contact resistances between superconducting tapes or by design. The interplay between contact and termination resistances is the defining factor for power dissipation in these cables and ultimately defines their safe operational margins. However, the current distribution between components along the composite conductor and inside its terminations is a priori unknown, and presently, no means are available to actively tune current flow distribution in real-time to improve margins of quench protection. Also, the lack of ability to electrically probe individual components makes it impossible to identify conductor damage locations within the cable. In this work, we address both problems by introducing active current control of current distribution between components using cryogenically operated metal-oxide-semiconductor-field-effect transistors (MOSFETs). We demonstrate through simulation and experiments how real-time current controls can help to drastically reduce heat dissipation in a developing hot spot in a two-conductor model system and help identify critical current degradation of individual cable components. Finally, prospects of other potential uses of MOSFET devices for improved voltage detection, AC loss-driven active quench protection, and remnant magnetization reduction in HTS magnets are also discussed.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Electric Drive Technologies Consortium (EDTC)/ Cost competitive, high-Performance, highly Reliable (CPR) Power Devices on 4H-SiC (Final Report)

4H-Silicon carbide (4H-SiC) is a wide bandgap semiconductor that offers superior material properties over silicon, including higher critical electric field, thermal conductivity, and electron saturation velocity. These advantages make 4H-SiC highly attractive for high-voltage, high-efficiency power electronics. However, realizing the full potential of SiC requires device technologies that are not only high-performing but also manufacturable and reliable under real-world operating conditions. This report summarizes the outcomes of a five-year R&D effort funded by the U.S. Department of Energy (DOE) under the Electric Drive Technologies Consortium (EDTC), focused on developing cost-competitive, high-performance, and highly reliable (CPR) power devices on 4H-SiC substrates. The program targeted scalable and manufacturable 1.2 kV-class SiC MOSFETs optimized for next-generation electric vehicles, renewable energy systems, and industrial power conversion. The project delivered transformative advancements in SiC power device performance and ruggedness. Particularly, Specific on-resistance (R on,sp ) was reduced by up to 37%, from ~4.0 m$\Omega \cdot$cm 2 in earlier designs to an industry-leading 2.40 m$\Omega \cdot$cm 2 , driven by optimized doping, refined JFET widths, and layout engineering. Breakdown voltages (BV) exceeded 1600 V, marking improvement over legacy baselines, and demonstrating the robustness of newly implemented junction profiles and edge terminations. Short-circuit withstand time (SCWT) saw a remarkable 4$\times$ increase, from ~2 $\mu$s to over 8 $\mu$s, achieved through the successful deployment of deep P-well structures (~1.8–2.0 $\mu$m) via channeling implantation. This innovative process breakthrough enabled precise junction formation without MeV-class implantation tools, reduced leakage under high field stress, and allowed even the shortest-channel devices (down to 0.3 $\mu$m) to achieve both high BV and excellent ruggedness—breaking the traditional trade-off between conduction efficiency and blocking capability. Several novel architectures pushed the performance envelope further. JBSFETs—featuring embedded Schottky portions—eliminated bipolar degradation and drastically reduced third-quadrant leakage, while Ladder MOSFETs introduced a clever orthogonal conduction path that achieved a 15.4% reduction in R on,sp over standard linear designs. Switching performance reached new benchmarks: short-channel devices showed a 31% reduction in total switching energy compared to 0.5 $\mu$m counterparts, while maintaining manageable gate drive requirements. Layout-optimized structures not only improved transconductance but also accelerated switching transitions, pointing to real-world benefits in converter-level efficiency. The devices also passed rigorous reliability validation. Stress-tested across TDDB, HTGB, HTRB, HVP, and burn-in, the devices screened under 30 V/10 hr and 43 V/1 s protocols consistently exhibited tighter lifetime distributions and long-term oxide robustness. These screening techniques proved effective in identifying latent defects and ensuring deployment-grade reliability. Meanwhile, advanced 3D TCAD simulations revealed and resolved electric field hotspots—particularly in HEXFET corners—where fields exceeding 4.8 MV/cm were mitigated through geometry-aware layout corrections. Overall, the results of this project demonstrate a manufacturable and scalable SiC power device platform that addresses key DOE performance targets for efficient, robust, and reliable 1.2kV 4H-SiC Power Devices. The developed technologies represent a meaningful step forward in the commercial readiness of high-voltage SiC solutions and provide a strong foundation for continued advancement in wide bandgap power electronics.

42 ENGINEERING↗
DOE OSTI2026

Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective

The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.

gate-all-around transistors↗