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Results for “MEMORY STORAGE UNIT”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records

All sources NASA NTRS DOE OSTI

DOE OSTI2013

Distributed trace using central performance counter memory

A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2013

Distributed trace using central performance counter memory

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Ultra-low power processor-in-memory architecture

An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.

DeBenedictis, Erik↗

DOE OSTI2018

Device and methods for writing and erasing analog information in small memory units via voltage pulses

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

42 ENGINEERING↗

DOE OSTI2022

Low-power anisotropic molecular electronic memristors

A molecular electronic memristor, programmable resistive memory device, promises to revolutionize next-generation flexible data storage units, offering fast, dense and ultralow power solutions. Here we report anisotropic resistive switching in molecular κ-(BEDT-TTF) 2 Cu[N(CN) 2 ]Cl memristors, consisting of alternatively segregated bis(ethylenedithio)tetrathiafulvalene (BEDT-TTF) and Cu[N(CN) 2 ]Cl layers. Electron resistance switching behavior controlled by charge tunneling in molecular memristors show a low set voltage of 0.5 V (10 V/cm) with the ON/OFF ratio of 2.3×10 3 along a-axis and a high-level endurance of 1.25×10 4 cycles along all axes. Finally, the findings of such molecular electronic crystals promise for low-power data storage memristors.

36 MATERIALS SCIENCE↗

DOE OSTI2013

Systems and methods to control multiple peripherals with a single-peripheral application code

Methods and apparatus are provided for enhancing the BIOS of a hardware peripheral device to manage multiple peripheral devices simultaneously without modifying the application software of the peripheral device. The apparatus comprises a logic control unit and a memory in communication with the logic control unit. The memory is partitioned into a plurality of ranges, each range comprising one or more blocks of memory, one range being associated with each instance of the peripheral application and one range being reserved for storage of a data pointer related to each peripheral application of the plurality. The logic control unit is configured to operate multiple instances of the control application by duplicating one instance of the peripheral application for each peripheral device of the plurality and partitioning a memory device into partitions comprising one or more blocks of memory, one partition being associated with each instance of the peripheral application. The method then reserves a range of memory addresses for storage of a data pointer related to each peripheral device of the plurality, and initializes each of the plurality of peripheral devices.

Ransom, Ray M.↗

DOE OSTI2013

Systems and methods to control multiple peripherals with a single-peripheral application code

42 ENGINEERING↗

DOE OSTI2026

Exploring Offshore Regional Atlantic Carbon Storage and Infrastructure for Eastern USA (Supporting Communities and Industry for Mid-Atlantic Offshore Carbon Storage Hub)

This final technical report presents a summary of work completed for the project Supporting Communities and Industry for Mid-Atlantic Offshore Carbon Storage Hub (FE0032407), which has been designated EXPLORE-ACS (Exploring Potential Long-Term Offshore Regional Atlantic Carbon Storage). The project is part of the U.S. Department of Energy (DOE) National Energy Technology Laboratory (NETL) funding opportunity announcement 2799 for Regional Initiatives to Accelerate Carbon Capture, Utilization, and Storage (CCUS) Deployment. The objective of the DOE 2799 program is to identify and address the challenges facing commercial deployment of carbon capture, transport, and storage in specific regions of the United States.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗

DOE OSTI2015

System, methods and apparatus for program optimization for multi-threaded processor architectures

Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least two multi-stage execution units that allow for parallel execution of tasks. The first custom computing apparatus optimizes the code for parallelism, locality of operations and contiguity of memory accesses on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

42 ENGINEERING↗

DOE OSTI2023

Single-shot switching in Tb/Co-multilayer based nanoscale magnetic tunnel junctions

Magnetic tunnel junctions (MTJs) are elementary units of magnetic memory devices. For high-speed and low-power data storage and processing applications, fast reversal of the magnetization by an ultrashort laser pulse is extremely important. Here we demonstrate single-shot switching of Tb/Co-multilayer based nanoscale MTJs by combining the optical writing and the electrical read-out methods. A 90-fs-long laser pulse switches the magnetization of the storage layer (SL). The change in the tunneling magnetoresistance (TMR) between the SL and a reference layer (RL) is probed electrically across the oxide barrier. Single-shot switching is demonstrated by varying the cell diameter from 300 nm to 20 nm. The anisotropy, magnetostatic coupling, and switching probability exhibit cell-size dependence. By suitable association of laser fluence and magnetic field, successive commutation between high-resistance and low-resistance states is achieved. The nature of the magnetization reversal of both SL and RL in a continuous film is probed with a depth-resolved magneto-optical Kerr effect (MOKE) magnetometry. The ultrafast dynamics in the continuous full-MTJ stack is investigated with the time-resolved pump–probe technique. Our experimental findings provide strong support for the growing interest in ultrafast spintronic devices.

36 MATERIALS SCIENCE↗

DOE OSTI2025

MRCI - Final Technical Report

The objective of the Midwest Regional Carbon Initiative (MRCI) project was to implement a collaborative Regional Initiative to accelerate the deployment of carbon capture, utilization, and storage (CCUS) in the Midwest-Northeastern and Mid-Atlantic areas of the United States. This area encompasses a 20-state region with much of the country’s carbon dioxide (CO2) emissions. The MRCI project is co-led by Battelle Memorial Institute (Battelle) in Columbus, Ohio, and the Illinois State Geological Survey (ISGS) in Champaign, Illinois, and benefitted from the experience these organizations have acquired over the past 10-plus years leading two Department of Energy (DOE) Regional Carbon Sequestration Partnerships (RCSPs): the Midwestern Regional Carbon Sequestration Partnership (MRCSP), led by Battelle, and the Midwest Geologic Sequestration Consortium (MGSC), led by the ISGS.

CCS↗

DOE OSTI2018

PIMS: Memristor-Based Processing-in-Memory-and-Storage.

Continued progress in computing has augmented the quest for higher performance with a new quest for higher energy efficiency. This has led to the re-emergence of Processing-In-Memory (PIM) ar- chitectures that offer higher density and performance with some boost in energy efficiency. Past PIM work either integrated a standard CPU with a conventional DRAM to improve the CPU- memory link, or used a bit-level processor with Single Instruction Multiple Data (SIMD) control, but neither matched the energy consumption of the memory to the computation. We originally proposed to develop a new architecture derived from PIM that more effectively addressed energy efficiency for high performance scientific, data analytics, and neuromorphic applications. We also originally planned to implement a von Neumann architecture with arithmetic/logic units (ALUs) that matched the power consumption of an advanced storage array to maximize energy efficiency. Implementing this architecture in storage was our original idea, since by augmenting storage (in- stead of memory), the system could address both in-memory computation and applications that accessed larger data sets directly from storage, hence Processing-in-Memory-and-Storage (PIMS). However, as our research matured, we discovered several things that changed our original direc- tion, the most important being that a PIM that implements a standard von Neumann-type archi- tecture results in significant energy efficiency improvement, but only about a O(10) performance improvement. In addition to this, the emergence of new memory technologies moved us to propos- ing a non-von Neumann architecture, called Superstrider, implemented not in storage, but in a new DRAM technology called High Bandwidth Memory (HBM). HBM is a stacked DRAM tech- nology that includes a logic layer where an architecture such as Superstrider could potentially be implemented.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- V TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- V TH state write, but also depletion charge for low- V TH state programming, though with lower efficiency; and 3) during the low/high- V TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- V TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- V TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

FeFET↗

DOE OSTI2026

Light storage, retrieval, and controllable interference in an atomic tripod system

Highly efficient quantum memories are essential for advancing quantum information processing technologies, including scalable quantum computing and quantum networks. We experimentally demonstrate a light storage and retrieval protocol in a tripod system using an ensemble of laser-cooled 87 Rb atoms. The tripod system, which consists of three ground states and an excited state, offers rich dynamics: its use to coherently store and retrieve a weak probe pulse in the 87 Rb 𝐹 = 1 ground-state manifold leads to the interference of two spin-wave excitations during storage time that translate to an interference in the peak intensity of the retrieved probe pulse. Our work shows that these interferences, which manifest when varying the pulse sequence or energy level structure, can be controlled experimentally by varying the storage time, optical phase, and magnetic field strength. Theoretical simulations exhibit excellent agreement with the experimental results. In conclusion, this work demonstrates the rich dynamics and versatile capabilities of atomic tripod systems for light storage and retrieval, with key advantages over conventional Λ systems, highlighting the potential of atomic tripod systems for applications in quantum information processing, quantum synchronization, and atomic memory protocols.

Coherent control↗

DOE OSTI2024

Nonvolatile electrochemical memory at 600°C enabled by composition phase separation

Silicon-based microelectronics are limited to ~150°C and therefore not suitable for the extremely high temperatures in aerospace, energy, and space applications. While wide-band-gap semiconductors can provide high-temperature logic, nonvolatile memory devices at high temperatures have been challenging. In this work, we develop a nonvolatile electrochemical memory cell that stores and retains analog and digital information at temperatures as high as 600°C. Through correlative scanning transmission electron microscopy, we show that this high-temperature information retention is a result of composition phase separation between the oxidized and reduced forms of amorphous tantalum oxide. This result demonstrates a memory concept that is resilient at extreme temperatures and reveals phase separation as the principal mechanism that enables nonvolatile information storage in these electrochemical memory cells.

42 ENGINEERING↗

DOE OSTI2023

Design and implementation of I/O performance prediction scheme on HPC systems through large-scale log analysis

Abstract Large-scale high performance computing (HPC) systems typically consist of many thousands of CPUs and storage units used by hundreds to thousands of users simultaneously. Applications from large numbers of users have diverse characteristics, such as varying computation, communication, memory, and I/O intensity. A good understanding of the performance characteristics of each user application is important for job scheduling and resource provisioning. Among these performance characteristics, I/O performance is becoming increasingly important as data sizes rapidly increase and large-scale applications, such as simulation and model training, are widely adopted. However, predicting I/O performance is difficult because I/O systems are shared among all users and involve many layers of software and hardware stack, including the application, network interconnect, operating system, file system, and storage devices. Furthermore, updates to these layers and changes in system management policy can significantly alter the I/O behavior of applications and the entire system. To improve the prediction of the I/O performance on HPC systems, we propose integrating information from several different system logs and developing a regression-based approach to predict the I/O performance. Our proposed scheme can dynamically select the most relevant features from the log entries using various feature selection algorithms and scoring functions, and can automatically select the regression algorithm with the best accuracy for the prediction task. The evaluation results show that our proposed scheme can predict the write performance with up to 90% prediction accuracy and the read performance with up to 99% prediction accuracy using the real logs from the Cori supercomputer system at NERSC.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Optimizing Management of Persistent Data Structures in High-Performance Analytics

Large-scale data analytics workflows ingest massive input data into various data structures, including graphs and key-value datastores. These data structures undergo multiple transformations and computations and are typically reused in incremental and iterative analytics workflows. Persisting in-memory views of these data structures enables reusing them beyond the scope of a single program run while avoiding repetitive raw data ingestion overheads. Memory-mapped I/O enables persisting in-memory data structures without data serialization and deserialization overheads. However, memory-mapped I/O lacks the key feature of persisting consistent snapshots of these data structures for incremental ingestion and processing. The obstacles to efficient virtual memory snapshots using memory-mapped I/O include background writebacks outside the application’s control, and the significantly high storage footprint of such snapshots. To address these limitations, we present Privateer, a memory and storage management tool that enables storage-efficient virtual memory snapshotting while also optimizing snapshot I/O performance. Here, we integrated Privateer into Metall, a state-of-the-art persistent memory allocator for C++, and the Lightning Memory-Mapped Database (LMDB), a widely-used key-value datastore in data analytics and machine learning. Privateer optimized application performance by 1.22× when storing data structure snapshots to node-local storage, and up to 16.7× when storing snapshots to a parallel file system. Privateer also optimizes storage efficiency of incremental data structure snapshots by up to 11× using data deduplication and compression.

Computer science↗

DOE OSTI2025

Curvature Memory in Electrically Stimulated Lipid Membranes

Here, we demonstrate, using non-equilibrium molecular dynamics simulations, that lipid membrane capacitance varies with surface charge accumulation linked to membrane shape and curvature changes. Specifically, we show that lipid membranes exhibit a hysteretic response when exposed to oscillatory electric fields. The electromechanical coupling in these membranes leads to hysteretic buckling, in which the membrane can spontaneously buckle in one of two distinct directions along the electric field, even for the same ionic charge accumulation at the water–membrane interface. In this regard, these binary buckled membrane states suggest potential applications in neuromorphic computing. Their bistable nature, characterized by two distinct and stable configurations, could serve as a foundation for implementing memory storage systems and logic operations. Furthermore, we introduce a circuit model that captures these dynamic effects, offering insights into emergent memory effects in electrically stimulated lipid membranes. Finally, this work presents lipid bilayers as dynamic, adaptable elements and suggests a new platform for exploring energy storage, information processing, and memory encoding at the lipid membrane level.

59 BASIC BIOLOGICAL SCIENCES↗