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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Incipient fault detection and power system protection for spaceborne systems

A program was initiated to study the feasibility of using advanced terrestrial power system protection techniques for spacecraft power systems. It was designed to enhance and automate spacecraft power distribution systems in the areas of safety, reliability and maintenance. The proposed power management/distribution system is described as well as security assessment and control, incipient and low current fault detection, and the proposed spaceborne protection system. It is noted that the intelligent remote power controller permits the implementation of digital relaying algorithms with both adaptive and programmable characteristics.

Russell, B. Don↗
NASA NTRS2003

Detection of High-impedance Arcing Faults in Radial Distribution DC Systems

High voltage, low current arcing faults in DC power systems have been researched at the NASA Glenn Research Center in order to develop a method for detecting these 'hidden faults', in-situ, before damage to cables and components from localized heating can occur. A simple arc generator was built and high-speed and low-speed monitoring of the voltage and current waveforms, respectively, has shown that these high impedance faults produce a significant increase in high frequency content in the DC bus voltage and low frequency content in the DC system current. Based on these observations, an algorithm was developed using a high-speed data acquisition system that was able to accurately detect high impedance arcing events induced in a single-line system based on the frequency content of the DC bus voltage or the system current. Next, a multi-line, radial distribution system was researched to see if the arc location could be determined through the voltage information when multiple 'detectors' are present in the system. It was shown that a small, passive LC filter was sufficient to reliably isolate the fault to a single line in a multi-line distribution system. Of course, no modification is necessary if only the current information is used to locate the arc. However, data shows that it might be necessary to monitor both the system current and bus voltage to improve the chances of detecting and locating high impedance arcing faults

Gonzalez, Marcelo C.↗
NASA NTRS1997

Nickel-Hydrogen Battery Fault Clearing at Low State of Charge

Fault clearing currents were achieved and maintained at discharge rates from C/2 to C/3 at high and low states of charge. The fault clearing plateau voltage is strong function of: discharge current, and voltage-prior-to-the-fault-clearing-event and a weak function of state of charge. Voltage performance, for the range of conditions reported, is summarized.

Lurie, C.↗
NASA NTRS1998

An Analysis of Failure Handling in Chameleon, A Framework for Supporting Cost-Effective Fault Tolerant Services

The desire for low-cost reliable computing is increasing. Most current fault tolerant computing solutions are not very flexible, i.e., they cannot adapt to reliability requirements of newly emerging applications in business, commerce, and manufacturing. It is important that users have a flexible, reliable platform to support both critical and noncritical applications. Chameleon, under development at the Center for Reliable and High-Performance Computing at the University of Illinois, is a software framework. for supporting cost-effective adaptable networked fault tolerant service. This thesis details a simulation of fault injection, detection, and recovery in Chameleon. The simulation was written in C++ using the DEPEND simulation library. The results obtained from the simulation included the amount of overhead incurred by the fault detection and recovery mechanisms supported by Chameleon. In addition, information about fault scenarios from which Chameleon cannot recover was gained. The results of the simulation showed that both critical and noncritical applications can be executed in the Chameleon environment with a fairly small amount of overhead. No single point of failure from which Chameleon could not recover was found. Chameleon was also found to be capable of recovering from several multiple failure scenarios.

Haakensen, Erik Edward↗
NASA NTRSDate not supplied

Design and Testing of a Hard-Fault Protection Circuit for a 1 kV SiC MOSFET Inverter

Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to prevent exceeding the current rating of these devices during low-inductance fault events. This paper explores the use of an air core Rogowski coil topology to mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-to-phase fault in under one microsecond, tested up to DC link voltages of 1 kV. This paper details the theory, design, simulation, and successful test results of this method.

hard fault protection↗
NASA NTRS1983

Source circuit design considerations

The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.

Noel, G. T.↗
NASA NTRS1966

Circuit protects regulated power supply against overload current

Sensing circuit in which a tunnel diode controls a series regulator transistor protects a low voltage transistorized dc regulator from damage by excessive load currents. When a fault occurs, the faulty circuit is limited to a preset percentage of the current when limiting first occurs.

Airth, H. B.↗
NASA NTRS1994

Fault tolerant onboard packet switch architecture for communication satellites: Shared memory per beam approach

The NASA Lewis Research Center is developing a multichannel communication signal processing satellite (MCSPS) system which will provide low data rate, direct to user, commercial communications services. The focus of current space segment developments is a flexible, high-throughput, fault tolerant onboard information switching processor. This information switching processor (ISP) is a destination-directed packet switch which performs both space and time switching to route user information among numerous user ground terminals. Through both industry study contracts and in-house investigations, several packet switching architectures were examined. A contention-free approach, the shared memory per beam architecture, was selected for implementation. The shared memory per beam architecture, fault tolerance insertion, implementation, and demonstration plans are described.

Shalkhauser, Mary JO↗
NASA NTRS2001

Adjustable Autonomy Testbed

The Adjustable Autonomy Testbed (AAT) is a simulation-based testbed located in the Intelligent Systems Laboratory in the Automation, Robotics and Simulation Division at NASA Johnson Space Center. The purpose of the testbed is to support evaluation and validation of prototypes of adjustable autonomous agent software for control and fault management for complex systems. The AA T project has developed prototype adjustable autonomous agent software and human interfaces for cooperative fault management. This software builds on current autonomous agent technology by altering the architecture, components and interfaces for effective teamwork between autonomous systems and human experts. Autonomous agents include a planner, flexible executive, low level control and deductive model-based fault isolation. Adjustable autonomy is intended to increase the flexibility and effectiveness of fault management with an autonomous system. The test domain for this work is control of advanced life support systems for habitats for planetary exploration. The CONFIG hybrid discrete event simulation environment provides flexible and dynamically reconfigurable models of the behavior of components and fluids in the life support systems. Both discrete event and continuous (discrete time) simulation are supported, and flows and pressures are computed globally. This provides fast dynamic simulations of interacting hardware systems in closed loops that can be reconfigured during operations scenarios, producing complex cascading effects of operations and failures. Current object-oriented model libraries support modeling of fluid systems, and models have been developed of physico-chemical and biological subsystems for processing advanced life support gases. In FY01, water recovery system models will be developed.

Malin, Jane T.↗
NASA NTRSDate not supplied

Hard Fault Protection for a Silicon Carbide-Based Aerospace Motor Drive

Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to protect these devices from overcurrent during low-inductance fault events. The use of an air core Rogowski coil topology was explored to see if it could mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-tophase fault, tested up to DC link voltages of 1 kV.

High Voltage↗
NASA NTRS1986

Fault and Error Latency Under Real Workload: an Experimental Study

A practical methodology for the study of fault and error latency is demonstrated under a real workload. This is the first study that measures and quantifies the latency under real workload and fills a major gap in the current understanding of workload-failure relationships. The methodology is based on low level data gathered on a VAX 11/780 during the normal workload conditions of the installation. Fault occurrence is simulated on the data, and the error generation and discovery process is reconstructed to determine latency. The analysis proceeds to combine the low level activity data with high level machine performance data to yield a better understanding of the phenomena. A strong relationship exists between latency and workload and that relationship is quantified. The sampling and reconstruction techniques used are also validated. Error latency in the memory where the operating system resides was studied using data on the physical memory access. Fault latency in the paged section of memory was determined using data from physical memory scans. Error latency in the microcontrol store was studied using data on the microcode access and usage.

Chillarege, Ram↗
NASA NTRS2014

International Space Station (ISS) Plasma Contactor Unit (PCU) Utilization Plan Assessment Update

The International Space Station (ISS) vehicle undergoes spacecraft charging as it interacts with Earth's ionosphere and magnetic field. The interaction can result in a large potential difference developing between the ISS metal chassis and the local ionosphere plasma environment. If an astronaut conducting extravehicular activities (EVA) is exposed to the potential difference, then a possible electrical shock hazard arises. The control of this hazard was addressed by a number of documents within the ISS Program (ISSP) including Catastrophic Safety Hazard for Astronauts on EVA (ISS-EVA-312-4A_revE). The safety hazard identified the risk for an astronaut to experience an electrical shock in the event an arc was generated on an extravehicular mobility unit (EMU) surface. A catastrophic safety hazard, by the ISS requirements, necessitates mitigation by a two-fault tolerant system of hazard controls. Traditionally, the plasma contactor units (PCUs) on the ISS have been used to limit the charging and serve as a "ground strap" between the ISS structure and the surrounding ionospheric plasma. In 2009, a previous NASA Engineering and Safety Center (NESC) team evaluated the PCU utilization plan (NESC Request #07-054-E) with the objective to assess whether leaving PCUs off during non-EVA time periods presented risk to the ISS through assembly completion. For this study, in situ measurements of ISS charging, covering the installation of three of the four photovoltaic arrays, and laboratory testing results provided key data to underpin the assessment. The conclusion stated, "there appears to be no significant risk of damage to critical equipment nor excessive ISS thermal coating damage as a result of eliminating PCU operations during non- EVA times." In 2013, the ISSP was presented with recommendations from Boeing Space Environments for the "Conditional" Marginalization of Plasma Hazard. These recommendations include a plan that would keep the PCUs off during EVAs when the space environment forecast input to the ISS charging model indicates floating potentials (FP) within specified limits. These recommendations were based on the persistence of conditions in the space environment due to the current low solar cycle and belief in the accuracy and completeness of the ISS charging model. Subsequently, a Noncompliance Report (NCR), ISS-NCR-232G, Lack of Two-fault Tolerance to EVA Crew Shock in the Low Earth Orbit Plasma Environment, was signed in September 2013 specifying new guidelines for the use of shock hazard controls based on a forecast of the space environment from ISS plasma measurements taken prior to the EVA [ISS-EVA-312-AC, 2012]. This NESC assessment re-evaluates EVA charging hazards through a process that is based on over 14 years of ISS operations, charging measurements, laboratory tests, EMU studies and modifications, and safety reports. The assessment seeks an objective review of the plasma charging hazards associated with EVA operations to determine if any of the present hazard controls can safely change the PCU utilization plan to allow more flexibility in ISS operations during EVA preparation and execution.

Hernandez-Pellerano, Amri↗
NASA NTRS1977

Extended performance solar electric propulsion thrust system study. Volume 5. Capacitor-diode voltage multiplier: Technology evaluation

A 1-kW capacitor-diode voltage multiplier (CDVM) was designed, fabricated and tested to demonstrate the power of feasibility of high power CDVM's and to verify the analytical techniques that had been used to predict the performance characteristics of a 6-kw CDVM. High efficiency (96.2%), a low ratio of component weight to power (0.55 kg/kW), and low output ripple voltage (less than 1%, peak to peak) were obtained during the operation of a 1-kW CDVM various input line, load current, and load fault conditions.

Martinelli, R. M.↗
NASA NTRS1976

Solid state remote power controllers for 120 Vdc power systems

Solid state Remote Power Controllers (RPCs) developed for use in any dc power system with voltage up to 120 Vdc and distributed power up to 3.6 kW per bus are described. The RPCs were demonstrated to be reliable, 99 percent efficient, comparatively simple, and potentially low in cost. Advantages of the RPCs include: contactless switching; controlled rates of current rise and fall; current limiting; and fast, well-defined, repeatable response to overloads and faults.

Sundberg, G. R.↗
NASA NTRS1993

Correct CMOS IC defect models for quality testing

Leading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.

Soden, Jerry M.↗
NASA NTRS2019

New Test Rig to Measure Alternating Current Losses of Both Low and High Critical Temperature Superconductors

This paper presents the design, development, operation, and test capabilities of a proposed superconducting coil testbed to measure alternating current (AC) losses at the NASA Glenn Research Center. Superconducting AC losses are important in the design of electric stators and rotors, power transmission lines, transformers, fault current limiters, magnets, and superconducting energy storage (not batteries). The new liquid-hydrogen-based rig will allow superconducting testing across a wide range of test parameters, including injected current up to 400 A, frequency (0 to 400 Hz), magnetic field (0 to 0.6 T), phase angle between induced voltage and injected current (–180° to 180°), coil coolant temperature (18 to 28 K), and AC power loss (5 to 30 W). While the target application of interest is 20 K superconducting MgB2 (the only superconductor that can presently be made with low losses) stator coils for future electric machines, the rig can accommodate test articles (TAs) with straight wire, tape, cables, coils of any shape, any allowable combination of superconducting wire and fluid (e.g., yttrium barium copper oxide (YBCO) coils and liquid nitrogen), and AC or direct current (DC) testing. The new spin rig builds upon the existing Air Force spin rig through a more flexible mode of fluid control, a wider gap space (up to 10.2 cm) for TAs, and the ability to accommodate TAs over a wider range of operating temperatures (18 to 95 K) using liquid hydrogen, gaseous helium, or liquid nitrogen as the working fluid, thus supporting direct cooled machines below 77 K.

liquid hydrogen↗
NASA NTRS1993

Nuclear propulsion control and health monitoring

An integrated control and health monitoring architecture is being developed for the Pratt & Whitney XNR2000 nuclear rocket. Current work includes further development of the dynamic simulation modeling and the identification and configuration of low level controllers to give desirable performance for the various operating modes and faulted conditions. Artificial intelligence and knowledge processing technologies need to be investigated and applied in the development of an intelligent supervisory controller module for this control architecture.

Walter, P. B.↗
NASA NTRS1979

A high performance microcomputer for space applications

This paper presents a description of a high-performance single board LSI microprocessor (the ATAC-16MS), which forms the core of the attitude and articulation control system of the Galileo spacecraft. The requirements of high speed, low power (20 watts), high reliability and radiation immunity are discussed in terms of the resulting implementation and trade-offs. The problems involved in the transition of a currently operational, fully-militarized processor into a space-qualified processor are summarized. System considerations for the effective use of the ATAC-16MS are also discussed, including the dual block-redundant architecture, the selective application of power for fault isolation and the trade-offs between low power dissipation and high performance of the peripheral circuitry for space applications.

Jack, L.↗