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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Magnetic flux imaging in a 3D superconductor integrated circuit

We report on imaging magnetic flux distributions in a multilayered superconductor integrated circuit which emerge during magnetization and after field cooling of the circuit in the DC magnetic field. The obtained complicated field maps expose the flux propagation across the patterned superconducting ground planes sandwiching layers with Josephson junction-based logic cells, fine wire grid around the functional units, and multiple superconducting fill structures located in different inner layers. The observed intricate flux distributions are explained by specific patterns of Meissner screening currents and superconducting critical currents in different mutually interacting parts of the integrated circuit. Our results provide important insights into possible ways of improving the protection of superconductor integrated circuits from magnetic fields and their resilience against flux trapping.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0

This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).

Shalf, JohnM. [Lawrence Berkeley National Laborato↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2026

Optical nanofiber testbeds for benchmarking membrane-waveguide photonic integrated circuit platforms toward on-chip quantum inertial sensing

Recent advances in cold atom interferometry with optical and magnetic atom guides have set the stage for quantum inertial sensors capable of operating in dynamic environments. In this work, we present three key innovations—evanescent-field (EF) atom guides, optical nanofiber testbeds, and membrane-waveguide photonic integrated circuit (PIC) platforms—to advance EF-guided atom interferometry. First, we demonstrate EF atom guides on optical nanofiber testbeds, which serve as performance benchmarks for our membrane-waveguide PIC platforms. Second, we achieve low-power (⁠ ~ 5 mW) guiding of freely moving, laser-cooled 133 Cs atoms in two-color, traveling-wave EF optical dipole traps at the novel, heat-efficient magic wavelengths of 793 and 937 nm (i.e., “793/937-nm EF atom guides”). Concurrently, we design and fabricate membrane-waveguide PIC platforms for these EF atom guides; in our prior work, we showed that these structures safely accommodate 4–6 times the required optical trap power under vacuum and enable dense cold atom generation via magneto-optical trapping in the vicinity of the optical wavguide for efficient loading. Third, we verify preserved atomic coherence via microwave fields and EF-coupled Doppler-free Raman beams; to our knowledge, this is the first report of coherence fringes driven by co-propagating EF-coupled Raman beams with only 150 nW of total optical power. By providing a direct comparison between optical nanofiber testbeds and membrane-waveguide PIC platforms, our results lay critical groundwork for the on-chip realization of EF-guided atom interferometry and the development of fully integrated, compact, lightweight, and low-power quantum accelerometers and gyroscopes.

Orozco, Adrian [Sandia National Laboratories (SNL-↗
DOE OSTI2025

Growth and structure of alpha-Ta films for quantum circuit integration

Tantalum films incorporated into superconducting circuits have exhibited low surface losses, resulting in long-lived qubit states. The remaining loss pathways originate in microscopic defects that manifest as two level systems (TLSs) at low temperatures. These defects limit performance, so careful attention to tantalum film structures is critical for optimal use in quantum devices. In this work, we investigate the growth of tantalum using magnetron sputtering on sapphire, Si, and photoresist substrates. In the case of sapphire, we present procedures for the growth of fully-oriented films with α-Ta [1 1 1]//Al2O3 [0 0 0 1] and α-Ta [1 −1 0]//Al2O3 [1 0 −1 0] orientational relationships and having residual resistivity ratio (RRR) ∼ 60 for 220 nm thick films. On Si, we find a complex grain texturing with Ta [1 1 0] normal to the substrate and RRR ∼ 30. We further demonstrate airbridge fabrication using Nb to nucleate α-Ta on photoresist surfaces. For the films on sapphire, resonators show TLS-limited quality factors of 1.3 ± 0.3 × 106 at 10 mK (for a waveguide gap and conductor width of 3 and 6 μm, respectively). Structural characterization using scanning electron microscopy, x-ray diffraction, low temperature transport, secondary ion mass spectrometry, and transmission electron microscopy reveal the dependence of residual impurities and screw dislocation density on processing conditions. The results provide practical insights into the fabrication of advanced superconducting devices including qubit arrays and guide future works on crystallographically deterministic qubit fabrication.

42 ENGINEERING↗
DOE OSTI2025

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Alimonti, G↗
DOE OSTI2025

Ultra-high Bandwidth, Ultra-high Dynamic Range X-Ray Shock Characterization via Photonic Integrated Circuit

Nuclear weapon component assessment tests at the Z Machine rely on accurate X-ray yield measurements for model validation, design and analysis of component survivability, and source optimization. Yield measurement devices currently used do not provide the requisite certainty to enable accurate and efficient data analysis of test results, which leads to an increase in Z-shots required for evaluation, longer device development times, and higher operation costs. Additionally, current X-ray flux detectors lack high temporal resolution at the tails. Similarly, shock measurement techniques used for component assessment often lack the ability to spatially resolve wave behavior thereby limiting the ability to measure shock propagation dynamics needed to design the next generation of ND components. Here we present the development of a photonic micro-calorimeter and shock sensor consisting of meter-long waveguide spirals that are optomechanically coupled to X-ray absorbing layers to characterize yield and shock propagation at nanosecond timescales.

42 ENGINEERING↗
DOE OSTI2025

Delay-resolved spectroscopy in terahertz photonic circuits

Photonic integrated circuits incorporating intersubband transitions are ideal for mid-infrared and terahertz nanophotonics. However, the design of epitaxies has long been inhibited by two factors: the modest predictivity of ab initio theory and the absence of absolute intersubband gain and loss measurements under operating conditions. Existing measurements either yield inaccurate gain profiles or do not accurately assess dependence on frequency, bias, and temperature. Here, we present a delay-resolved absolute-referencing method for accurate gain evaluation without these limitations, addressing a long-standing challenge. By creating a photonic circuit that allows broadband pulses to traverse different lengths of a gain medium, we measure the absolute transmission of intersubband structures. Gain profiles match theoretical predictions at lower temperatures, with gain and dispersion clamping after lasing, and faster-than-expected degradation occurs at higher temperatures. Our approach provides a precise experimental evaluation of temperature-dependent gain performance and gives insight into optimizing temperature performance and frequency comb designs.

Optical spectroscopy↗
DOE OSTI2024

Final Technical Report - Rapid Surface Microanalysis using a Low Temperature Plasma

This project focused on improving our current understanding and scientific knowledge in the area of plasma-surface interactions and plasma assisted material synthesis related to advanced microelectronics and nanotechnology. Current challenges include: controlling the interaction of Low Temperature Plasma (LTP) with a single layer of atoms to manufacture integrated circuits, continued miniaturization of integrated circuits, LTP processing of material surfaces and thin films to enable industrial scale fabrication of advanced microelectronics, synthesis of new materials, nanomaterials, nanotubes, and complex materials, Technology developed in this subtopic is of value to either (i) enable scans of surfaces (~1 sq. cm area) using various microscopies (electron, optical, other) at high resolution (micron or sub-micron resolution) rapidly (hours or days rather than years to complete a high-resolution scan of such a large surface area), or (ii) enable scans of surfaces (~1 sq. cm area) using various microscopies (electron, optical, other) at relatively low resolution rapidly, then apply algorithms to select spots for micron-scale imaging. Sputtering occurs when particles of a solid material are ejected from its surface by energetic particles from a plasma. While the degradation of the solid material and the subsequent deposition of the ejected material onto vulnerable surfaces are the usual subjects of sputtering studies, plasma science has yet to be combined with sputtering to create new diagnostics devices and systems. Small changes in the design of the plasma discharge device make it possible to create broad plasma beams for rapid scanning or small plasma beams to obtain the distribution of ejected elements with micron resolution. In the high-resolution use, the ion flux is extracted from the gas-discharge plasma and focused by a spherical emission surface to micron sizes onto the target specimen, providing very local sputtering and local elemental analysis. We call this “self-focusing”. The radiation from the excited and ionized sputtered atoms is recorded by a spectrometer through a window and fiberglass cable and analyzed with standard software packages used for optical glow discharge spectroscopy. Computer simulations of beam formation were used to verify and optimize the designs to be tested. A prototype was designed, constructed, and used to start experiments of beam formation.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

Aligned carbon nanotubes for 1,000x improvement in computing (CRADA Final Report)

As part of the Cyclotron Road program, the Aligned Carbon team worked to improve and bring to market their technology to manufacture carbon nanotubes (CNTs) for integrated circuits. There are multiple applications which can benefit from the use of CNT based transistors in integrated circuits, including high performance computing, RF data transmission, and biosensing. Each of these applications faces a problem of poor starting CNT material to come to market. Aligned Carbon offers material with the highest ceiling of performance based around a fully aligned, uniform, on-wafer growth of CNTs and our proprietary purification process to remove metallic CNTs leaving only the semi-conducting ones behind. Further, Aligned Carbon has been guided by scalable manufacturing processes that will fit seamlessly into the integrated circuit foundry model of chip fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Nanophotonic waveguide chip-to-world beam scanning

A seamless chip-to-world photonic interface enables broad advancements in optical ranging, display, communication, computation and quantum information science. The ideal solution enables two-dimensional scanning of a diffraction-limited beam from anywhere on a photonic integrated circuit to a large number of resolvable spots. Current beam-scanning technologies are limited by a fundamental trade-off: photonic-integrated-circuits with diffractive optics offer scalability but have poor mode quality, whereas inertially limited micromechanical scanners provide high-quality beams but lack scalable integration. Here we report a photonic ski-jump—a nanoscale waveguide monolithically integrated on a piezoelectric cantilever—to overcome these limitations. It passively curls ~90° out-of-plane within a less-than-0.1 mm 2 footprint, emits a submicrometre, broadband diffraction-limited beam, and exhibits kilohertz-rate mechanical resonances with quality factors of over 10,000. Fabricated in a volume complementary metal–oxide–semiconductor (CMOS) foundry, our device enables scalable two-dimensional beam scanning. Driven on-resonance at CMOS-level voltages, it achieves a footprint-adjusted spot rate of 68.6 mega spots s –1 mm–², exceeding state-of-the-art micro-electro-mechanical systems mirrors by more than 50-fold, which is sufficient for one million pixels at 100 Hz from an approximately 1.5 mm diameter footprint. We demonstrate full-colour image and video projection, and single-photon initialization and readout from silicon vacancy centres in diamond. Finally, by demonstrating uniformity across a 64 ski-jump array, we establish a pathway to achieving greater than one gigaspot resolution at kilohertz rates within a sub-5-cm-diameter footprint, creating a seamless optical pipeline between integrated photonic processors and the free-space world.

Displays↗
DOE OSTI2025

One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics

Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.

2D electronics↗
DOE OSTI2025

Characterizing and Modeling the Influence of Geometry on the Performance of Superconducting Nanowire Cryotrons

The scaling of superconducting nanowire detectors to larger arrays is often limited by room-temperature-readout cabling. Cryogenic integrated circuits constructed from nanowire cryotrons, or nanocryotrons, can address this limitation by performing signal processing on chip. In this study, we characterize key performance metrics of the nanocryotron to elucidate its potential as a logical element in cryogenic integrated circuits and develop an electro-thermal model to connect material parameters with device performance. We find that the performance of the nanocryotron depends on the device geometry, and trade-offs are associated with optimizing the gain, jitter, and energy dissipation. Here, we demonstrate that nanocryotrons fabricated on niobium nitride can achieve a grey zone less than 210 nA wide for a 5 ns long input pulse corresponding to a maximum achievable gain of 48 dB, an energy dissipation of less than 20 aJ per operation, and a jitter of less than 60 ps.

Superconductor↗
DOE OSTI2026

Evaluation of an event-driven 3FI ASIC for spectroscopic X-ray detection with synchrotron radiation

The novel design and evaluation on the NSLS-II beamline of the 3FI application-specific integrated circuit (ASIC) bump-bonded to a simple, planar, 2D segmented silicon sensor are presented. The ASIC was developed for full-field fluorescence spectral X-ray imaging (3FI). It is a small-scale prototype that features a square array of 32 × 32 pixels, and the size of the pixels is 100 µm × 100 µm. The ASIC was implemented in a 65 nm CMOS integrated circuit fabrication process. Each pixel incorporates a charge-sensitive amplifier, a shaping filter, a discriminator, a peak detector and a sample-and-hold circuit, allowing detection of events and storage of signal amplitudes. The system operates in a frameless event-driven readout mode, outputting analog values for threshold-triggered events, allowing high-speed multi-element X-ray fluorescence data acquisition. The 3FI ASIC achieves per-channel spectrometric performance at a power consumption of only 200 µW per pixel, with nearly all dissipation confined to the analog front-end. An energy resolution is measured at the level of 308 eV full width at half-maximum (FWHM) at 8.04 keV (Cu Kα), and 138 eV FWHM at 3.69 keV (Ca Kα). This per-pixel capability makes the prototype suitable for in situ trace element microanalysis in biological and environmental studies. Moreover, the frameless architecture of the detector is designed to address limitations of conventional X-ray fluorescence microscopy, which typically requires mechanical scanning, by enabling continuous high-throughput data acquisition in future full-field implementations.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Tale of Two Domains: Cyber - Physical

As devices and systems continue to modernize and adopt integrated circuits, the use of cyber technology to deploy an application is the expectation. This deployment through cyber assets brings new cyber risk and cybersecurity is the practice of managing this risk. Cyber-risk is constantly changing due to the speed of technology advancement and the changing quality of the adversary. Cyber-Informed Engineering (CIE) mitigates cyber-risk through engineering controls where as the traditional practice of cybersecurity mitigates cyber-risk through cybersecurity controls. By clearly defining the cyber-physical boundary, engineering controls and cybersecurity controls can clearly demonstrate their complementary nature to provide layered defenses and successfully mitigate cyber-risk through independent controls. In this paper, a layered model of device decomposition of the the cyber-physical boundary is presented to provide clarity where engineering controls are used to reduce cyber-risk within the physics, functional materials, electronic, or integrated circuit layers and where cybersecurity controls are used to reduce cyber-risk within the machine code and application layers. By implementing both traditional cybersecurity controls and engineering controls, a more holistic approach to cybersecurity is achieved in protecting modern devices and systems, as well as a clear awareness in identifying, documenting, and authorizing the system’s cybersecurity protection scheme is achieved.

42 - ENGINEERING↗
DOE OSTI2025

PtCoO 2 for Scaled Interconnects

Copper (Cu) interconnects are an increasingly important bottleneck in integrated circuits due to energy consumption and latency caused by the notable increase in Cu resistivity as dimensions decrease, primarily due to electron scattering at surfaces. Herein, the potential of a directional conductor, PtCoO 2 , which has a low bulk resistivity and a distinctive anisotropic structure that mitigates electron surface scattering is showcased. Thin films of PtCoO 2 of various thicknesses are synthesized by molecular beam epitaxy (MBE) coupled with a postdeposition annealing process and the superior quality of PtCoO 2 films is demonstrated by multiple characterization techniques. The thickness‐dependent resistivity curve illustrates that PtCoO 2 significantly outperforms effective Cu (Cu with TaN barriers) and Ru in resistivity below 20.0 nm with a more than 6x reduction compared to effective Cu below 6.0 nm, having a value of only 6.32 μΩ cm at 3.3 nm. It is determined that grain boundary scattering can still be improved for even lower resistivities in this material system through a combination of experiments and theoretical simulations. PtCoO 2 is therefore a highly promising alternative material for future interconnect technologies promising lower resistivities, better stability, and significant improvements in energy efficiency and latency for advanced integrated circuits.

Li, Yansong [Department of Electrical Engineering ↗
DOE OSTI2026

IMPACT 2025-2026 Internship Poster

At Sandia National Laboratories, I developed a C++ program that converts printed circuit boards(PCB) and integrated circuits(IC) design files to be compatible for computed tomography (CT) simulations through Monte Carlo methods.

97 MATHEMATICS AND COMPUTING↗