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Results for “IC design verification”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sources NASA NTRS DOE OSTI

NASA NTRSDate not supplied

xEMU Integrated Communication System

For the past several years, the Exploration Extra-Vehicular Mobility Unit (xEMU) team at NASA’s Johnson Space Center (JSC) has focused on development and testing of the xEMU to support missions to the International Space Station (ISS) and a moon landing in 2024. In that context, this paper examines the development and detailed design of the xEMU Integrated Communication System (ICS). This paper outlines the challenging technical requirements, significant architectural trades, technical solutions required to overcome these challenges, and a status of the detailed design. The preliminary results of Design Verification Testing (DVT) as it relates to the ICS are also provided, along with a forward strategy for final maturation into a flight-ready design.

Ian Meginnis↗

NASA NTRS2016

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

JFET↗

NASA NTRSDate not supplied

The Roman Space Telescope Optical System: Status, Test, and Verification

The Nancy Grace Roman Space Telescope (“Roman”) was prioritized by the 2010 Decadal Survey in Astronomy & Astrophysics and is NASA’s next flagship observatory. Launching no earlier than 2026, Roman will explore the nature of dark energy, as well as expand the census of exoplanets in our galaxy via microlensing. Roman will also demonstrate key technology needed to image and spectrally characterize extra-solar planets. Roman’s large field of view, agile survey capabilities, and excellent stability enable these scientific objectives, yet present unique challenges for the design, test, and verification of its optical system. The Roman optical system comprises an optical telescope assembly (OTA) and two instruments: the primary science wide-field instrument (WFI) and a technology demonstration coronagraph instrument (CGI), and the instrument carrier (IC), which meters the OTA to each instrument. This paper presents a status of the optical system hardware as it begins integration and test (I&T), as well as describes key optical test, alignment, and verification activities as part of the I&T program.

space telescope↗

NASA NTRS1979

Interpretive computer simulator for the NASA Standard Spacecraft Computer-2 (NSSC-2)

An Interpretive Computer Simulator (ICS) for the NASA Standard Spacecraft Computer-II (NSSC-II) was developed as a code verification and testing tool for the Annular Suspension and Pointing System (ASPS) project. The simulator is written in the higher level language PASCAL and implented on the CDC CYBER series computer system. It is supported by a metal assembler, a linkage loader for the NSSC-II, and a utility library to meet the application requirements. The architectural design of the NSSC-II is that of an IBM System/360 (S/360) and supports all but four instructions of the S/360 standard instruction set. The structural design of the ICS is described with emphasis on the design differences between it and the NSSC-II hardware. The program flow is diagrammed, with the function of each procedure being defined; the instruction implementation is discussed in broad terms; and the instruction timings used in the ICS are listed. An example of the steps required to process an assembly level language program on the ICS is included. The example illustrates the control cards necessary to assemble, load, and execute assembly language code; the sample program to to be executed; the executable load module produced by the loader; and the resulting output produced by the ICS.

Smith, R. S.↗