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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Hardware-in-the-Loop Test Bed and Test Methodology for Microgrid Controller Evaluation

Increasing penetration levels of distributed energy resources are making the deployment of microgrids more feasible. Controllers that operate such microgrids are key to realizing the objectives of the microgrid owner or operator and there is a need to evaluate microgrid controller performance prior to field deployment. This paper describes a controller hardware-in-the-loop and power hardware-in-the-loop microgrid controller test bed that was designed and constructed to evaluate the capabilities of a microgrid controller for a proposed campus microgrid. This paper also presents a test methodology to evaluate microgrid controller functionality, and it describes how the controller was assessed through the application of different test scenarios. Results from the testing are presented to provide insight into the capabilities of the test bed.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2014

Examining System-Wide Impacts of Solar PV Control Systems with a Power Hardware-in-the-Loop Platform

High penetration levels of distributed solar PV power generation can lead to adverse power quality impacts such as excessive voltage rise, voltage flicker, and reactive power values that result in unacceptable voltage levels. Advanced inverter control schemes have been proposed that have the potential to mitigate many power quality concerns. However, closed-loop control may lead to unintended behavior in deployed systems as complex interactions can occur between numerous operating devices. In order to enable the study of the performance of advanced control schemes in a detailed distribution system environment, a Hardware-in-the-Loop (HIL) platform has been developed. In the HIL system, GridLAB-D, a distribution system simulation tool, runs in real-time mode at the Pacific Northwest National Laboratory (PNNL) and supplies power system parameters at a point of common coupling to hardware located at the National Renewable Energy Laboratory (NREL). Hardware inverters interact with grid and PV simulators emulating an operational distribution system and power output from the inverters is measured and sent to PNNL to update the real-time distribution system simulation. The platform is described and initial test cases are presented. The platform is used to study the system-wide impacts and the interactions of controls applied to inverters that are integrated into a simulation of the IEEE 8500-node test feeder, with inverters in either constant power factor control or active volt/VAR control. We demonstrate that this HIL platform is well-suited to the study of advanced inverter controls and their impacts on the power quality of a distribution feeder. Additionally, the results from HIL are used to validate GridLAB-D simulations of advanced inverter controls.

14 SOLAR ENERGY↗
DOE OSTI2019

Hardware MPI message matching: Insights into MPI matching behavior to inform design: Hardware MPI message matching

Here, this paper explores key differences of MPI match lists for several important United States Department of Energy (DOE) applications and proxy applications. This understanding is critical in determining the most promising hardware matching design for any given high-speed network. The results of MPI match list studies for the major open-source MPI implementations, MPICH and Open MPI, are presented, and we modify an MPI simulator, LogGOPSim, to provide match list statistics. These results are discussed in the context of several different potential design approaches to MPI matching–capable hardware. The data illustrate the requirements for different hardware designs in terms of performance and memory capacity. Finally, this paper's contributions are the collection and analysis of data to help inform hardware designers of common MPI requirements and highlight the difficulties in determining these requirements by only examining a single MPI implementation.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Interconnection Standard Grid-Support Function Evaluations Using an Automated Hardware-in-the-Loop Testbed

Grid operators are increasingly turning to advanced grid-support functions in distributed energy resources (DER) to assist with distribution circuit voltage regulation, bulk system frequency control, and power system protection. The U.S. DER certification standard, Underwriters Laboratories (UL) 1741, was revised in September 2016 to add test procedures for multiple grid-support functions. Sandia National Laboratories, SunSpec Alliance, and growing community of collaborators have undertaken a multiyear effort to create an open-source system validation platform (SVP) that automates DER interconnection and interoperability test procedures by communicating with grid simulators, photovoltaic (PV) simulators, data acquisition systems, and interoperable equipment under test. However, the power hardware required for generating the test conditions may be untenable for many organizations. In this paper, we discuss development of the SVP testing capabilities for UL 1741 tests utilizing a controller hardware-in-the-loop testbed that precludes the need for power hardware using a 34.5 kW Austrian Institute of Technology smart grid controller. Finally, analysis of normal ramp rate, soft start ramp rate, specified power factor, volt-VAr, and frequency-watt advanced grid functions, and the effectiveness of the UL 1741 test protocols are included.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS2001

Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the class of applications with moderate input-output data rates but large intermediate multi-thread data streams has been addressed and mitigated. This opens a new class of satellite image processing applications for bottleneck problems solution using RC technologies. The issue of a science algorithm level of abstraction necessary for RC hardware implementation is also described. Selected Matlab functions already implemented in hardware were investigated for their direct applicability to the GOES-8 application with the intent to create a library of Matlab and IDL RC functions for ongoing work. A complete class of spacecraft image processing applications using embedded re-configurable computing technology to meet real-time requirements, including performance results and comparison with the existing system, is described in this paper.

Kizhner, Semion↗
DOE OSTI2022

Modeling and Feedback Compensator Design for Power-Hardware-in-the-Loop System for Medium-Voltage Grid-Connected Power Converters

Hardware-in-the-loop (HIL) evaluation is a method in which the test subject is split into a physical part and a simulated part, and these parts are connected with interfaces to form a combined physical-numerical system. Power-hardware-in-the-loop (PHIL) systems, where actual hardware is connected to a real-time model, can exhibit issues of instability, inaccuracy and errors when operating in a closed-loop. The challenges of generating a PHIL setup are that, first, because of the limited dynamic response of the different parts of the system, the test results might be inaccurate, and, second, because of the high frequency noise introduced by the sensors to the closed-loop system, it can be difficult to design a compensator for the real-time emulator response, while stabilizing the closed-loop system at the same time. In this paper, different parts of a PHIL system are characterized, and the feedback compensator system design is proposed for the stable operation of the closed-loop PHIL system. The issues as observed in a PHIL system without any compensator are demonstrated using experimental results, and the effectiveness of a first order phase lead compensator is validated.

compensator design↗
DOE OSTI2018

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems

Fail-slow hardware is an under-studied failure mode. We present a study of 114 reports of fail-slow hardware incidents, collected from large-scale cluster deployments in 14 institutions. We show that all hardware types such as disk, SSD, CPU, memory, and network components can exhibit performance faults. We made several important observations such as faults convert from one form to another, the cascading root causes and impacts can be long, and fail-slow faults can have varying symptoms. From this study, we make suggestions to vendors, operators, and systems designers.

fail-slow↗
NASA NTRS1989

Space biology initiative program definition review. Trade study 5: Modification of existing hardware (COTS) versus new hardware build cost analysis

The JSC Life Sciences Project Division has been directly supporting NASA Headquarters, Life Sciences Division, in the preparation of data from JSC and ARC to assist in defining the Space Biology Initiative (SBI). GE Government Services and Horizon Aerospace have provided contract support for the development and integration of review data, reports, presentations, and detailed supporting data. An SBI Definition (Non-Advocate) Review at NASA Headquarters, Code B, has been scheduled for the June-July 1989 time period. In a previous NASA Headquarters review, NASA determined that additional supporting data would be beneficial to determine the potential advantages in modifying commercial off-the-shelf (COTS) hardware for some SBI hardware items. In order to meet the demands of program implementation planning with the definition review in late spring of 1989, the definition trade study analysis must be adjusted in scope and schedule to be complete for the SBI Definition (Non-Advocate) Review. The relative costs of modifying existing commercial off-the-shelf (COTS) hardware is compared to fabricating new hardware. An historical basis for new build versus modifying COTS to meet current NMI specifications for manned space flight hardware is surveyed and identified. Selected SBI hardware are identified as potential candidates for off-the-shelf modification and statistical estimates on the relative cost of modifying COTS versus new build are provided.

Jackson, L. Neal↗
DOE OSTI2019

Systematic Characterization of Power Hardware-in-the-Loop Evaluation Platform Stability: Preprint

This paper presents a systematic approach to characterize the stability of a power-hardware-in-the-loop (PHIL) platform, an important step in PHIL tests. Many existing works focus the stability assessments on the PHIL interface algorithm; however, this work considers all software and hardware subsystems that form the closed loop of the PHIL experiment and develops a complete closed-loop stability assessment. This assessment is developed in the context of a common framework that can be readily applied to other PHIL platforms. This paper presents methods for characterizing key PHIL subsystems toward obtaining transfer functions to be used for analysis. The systematic stability assessment approach is demonstrated for a case study involving PHIL testing of a solar inverter and validated using experimental data. assessment. This assessment is developed in the context of a common framework that can be readily applied to other PHIL platforms. This paper presents methods for characterizing key PHIL subsystems toward obtaining transfer functions to be used for analysis. The systematic stability assessment approach is demonstrated for a case study involving PHIL testing of a solar inverter and validated using experimental data.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

Power-Hardware-in-the-Loop Interfaces for Inverter-Based Microgrid Experiments Including Transitions

Microgrids continue to proliferate, particularly those that rely on inverter-based resources as the microgrid's voltage and frequency leader. Hardware-in-the-loop simulations can de-risk microgrid deployments, and therefore we need power-hardware-in-the-loop (PHIL) interfaces for grid-forming (GFM) inverters to enable simulations of seamless transitions between islanded and grid-connected operation. Such interfaces are particularly challenging when the inverters need to switch modes, i.e., between grid-following (GFL) and GFM as the microgrid transitions between grid-connected and islanded operation. This paper presents two PHIL interfaces for such microgrids and the preliminary experimental results.

experiments↗
DOE OSTI2019

Controller-Hardware-in-the-Loop Test Bed for Fast-Switching SiC-Based 50-kW PV Inverter

The recent advent of wideband gap power semiconductor devices will lay the path to the future power converters. These devices provide the advantage of high switching speed and lower losses. The high cost and high switching speeds of these devices provide a challenge in the development and validation of the fast switching inverter controls with accuracy of that of a hardware setup. In this paper an FPGA real-time simulator-based controller-hardware-in-the-loop (CHIL) testbed is used to verify the low-level and advanced inverter controls fast switching wide bandgap-based string photovoltaic inverter. The paper also includes development of the CHIL testbed, which is run at a time-step of 500 ns in order to implement 20 kHz switching frequency. The developed CHIL testbed is validated through experimental results from a three-phase, 50 kW, 480 VLLrms SiC devices based inverter.

14 SOLAR ENERGY↗
NASA NTRS2005

MSAP Hardware Verification: Testing Multi-Mission System Architecture Platform Hardware Using Simulation and Bench Test Equipment

The Multi-Mission System Architecture Platform (MSAP) project aims to develop a system of hardware and software that will provide the core functionality necessary in many JPL missions and can be tailored to accommodate mission-specific requirements. The MSAP flight hardware is being developed in the Verilog hardware description language, allowing developers to simulate their design before releasing it to a field programmable gate array (FPGA). FPGAs can be updated in a matter of minutes, drastically reducing the time and expense required to produce traditional application-specific integrated circuits. Bench test equipment connected to the FPGAs can then probe and run Tcl scripts on the hardware. The Verilog and Tcl code can be reused or modified with each design. These steps are effective in confirming that the design operates according specifications.

Crossin, Kent R.↗
DOE OSTI2017

Power Hardware-in-the-Loop Evaluation of PV Inverter Grid Support on Hawaiian Electric Feeders

As more grid-connected photovoltaic (PV) inverters become compliant with evolving interconnections requirements, there is increased interest from utilities in understanding how to best deploy advanced grid-support functions (GSF) in the field. One efficient and cost-effective method to examine such deployment options is to leverage power hardware-in-the-loop (PHIL) testing methods, which combine the fidelity of hardware tests with the flexibility of computer simulation. This paper summarizes a study wherein two Hawaiian Electric feeder models were converted to real-time models using an OPAL-RT real-time digital testing platform, and integrated with models of GSF capable PV inverters based on characterization test data. The integrated model was subsequently used in PHIL testing to evaluate the effects of different fixed power factor and volt-watt control settings on voltage regulation of the selected feeders using physical inverters. Selected results are presented in this paper, and complete results of this study were provided as inputs for field deployment and technical interconnection requirements for grid-connected PV inverters on the Hawaiian Islands.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2021

A Multi-Site Networked Hardware-in-Loop Platform for Evaluation of Interoperability and Distributed Intelligence at Grid-Edge

Electric power systems have experienced large increases in the number of intelligent, connected and controllable devices being deployed, leading to a high degree of distributed intelligence at the grid-edge. These devices, both utility-owned and consumer-owned, include but are not limited to: renewable generation sources, energy storage, remote switches, voltage regulators, and smart controllable loads such as electric vehicles. These new devices provide significant potential for increased operational flexibility that can be leveraged to achieve system reconfiguration, resiliency improvements, power quality improvements, and distribution system automation. However, there are two significant challenges that must be addressed before these assets can be leveraged for operations: interoperability and system level validation prior to deployment. Because of the complexity of distributed control systems, and their interactions with legacy centralized controls, a purely simulations-based approach for pre-deployment validation is not sufficient. It requires hardware-in-loop testing to emulate the operational hardware devices and evaluate their performance. Additionally, securely integrating multiple test facilities at utility operators and vendors might enable rapid scale-up of evaluation platforms, and remove the need for multiple expensive standalone installations. Presented in this paper, is the development of a multi-site evaluation platform that employs Advanced Distribution Management Systems (ADMS), distributed control devices, real-time hardware-in-loop assets, secure communication links, and protocol adapters. This platform uses standards-based approaches and open-source tools, and hence can serve as a template for other researchers and institutions to implement their multi-site evaluation frameworks for pre-deployment testing.

Essakiappan, Somasundaram↗
DOE OSTI2022

Power and Communications Hardware-in-the-Loop CPS Architecture and Platform for DER Monitoring and Control Applications: Preprint

The rapid growth of distributed energy resources (DERs) has prompted increasing interest in the monitoring and control of DERs through hybrid smart grid communications. The deployment of communications and computation has transformed the traditional physical power grid into a smart cyber-physical system (CPS). To fully understand the interdependency between physical grid and cyber netowrks, this study designed a power and communications hardware-in-the-loop (PCommHIL) CPS architecture, which enables the flexible verification of DER monitoring and control with hybrid communications architectures and Internet protocols. Design, development and case study of a PCommHIL testbed for the DER coordination are discussed in detail, and the proposed platform integrates DER devices, Advanced Metering Infrastructures (AMIs), and a suite of hybrid communications networks for distribution automation applications. Case study on DER situational awareness and Volt-Var control validates the efficacy of this proposed PCommHIL platform with hybrid communications designs. Results show that the HAN communication technologies play a critical role in hybrid designs and it is the bottleneck for DER applications. High performance communication technologies are highly recommended to be applied in the HAN for enhanced monitoring and real-time control of DERs.

AMIs↗