Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “GaN HEMT”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

An RC snubber design method to achieve optimized switching noise‐loss trade‐off of cascode GaN HEMTs

Abstract The cascode gallium nitride high electron mobility transistors (GaN HEMTs) are very vulnerable to self‐sustained turn‐off oscillation due to their cascode configuration. This paper presents a design approach for the RC snubber of cascode GaN HEMTs to achieve the optimized noise‐loss trade‐off. At first, an analytical model is proposed to describe the instability of cascode GaN HEMTs‐based test circuits utilizing RC snubber. Based on the model, an analytical approach is proposed to achieve two optimum RC snubber designs S1 and S2. The design S1 can satisfactorily dampen the oscillation with minimum switching losses. The design S2 achieves maximum effective damping on the oscillation at a minimized cost of additional power losses. In the end, the accuracy of the proposed model is validated by the double‐pulse test and good agreement is obtained.

Xue, Peng↗
DOE OSTI2023

Origin of Soft-Switching Output Capacitance Loss in Cascode GaN HEMTs at High Frequencies

Output capacitance (C OSS ) loss (E DISS ) is produced when the C OSS of a power device is charged and discharged, which ideally should be a lossless process. This loss was recently revealed to be a crucial concern for GaN high electron mobility transistors (HEMTs) in high-frequency soft-switching applications. Among various GaN devices, the composite-type, cascode GaN HEMT was reported to show the largest E DISS with a voltage dependence distinct from discrete GaN HEMTs. However, the physical origins of the EDISS in cascode GaN HEMTs remain unclear. This work fills this gap by identifying three loss components and, for the first time, experimentally quantifying them in the multi-MHz resonant switching. These loss components include a) the avalanche loss of Si MOSFET, b) the intrinsic E DISS of GaN HEMT, and c) the Si avalanche-induced GaN turn-ON loss. The last component was found to dominate E DISS at high voltage. By eliminating the Si avalanche and the associated loss components (a) and (c), the E DISS of cascode GaN HEMTs can be reduced by up to 75% at the price of an increase in output charge and switching transition time. Furthermore, these results provide new physical insights and practical guidelines to trim the soft-switching loss of cascode GaN HEMTs in high-frequency applications.

42 ENGINEERING↗
DOE OSTI2020

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. Furthermore, these results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.

42 ENGINEERING↗
DOE OSTI2022

GaN HEMT Fabrication for Radiation-Hardened Sensing and Communications Electronics

Gallium nitride (GaN), a wide bandgap semiconductor, has vast potential to address two environment conditions associated with the application of electronics to nuclear power: elevated temperatures, and high levels of radiation. A process was developed at The Ohio State University (OSU) to enable fabrication of complex digital and analog electronics circuits for application to nuclear power environments such as locations near or in the reactor core or in spent nuclear fuel casks. Radio frequency (RF)-grade GaN high electron mobility transistor (HEMT) devices were fabricated as part of this process. These were fabricated as depletion mode and enhancement mode devices. They have been electrically characterized and have demonstrated the expected performance. Behavioral models (Verilog-A) were developed from these device measurements to enable electrical simulation of GaN HEMT devices and circuits using common electronics simulation tools based on Simulation Program with Integrated Circuit Emphasis (SPICE). A similar set of GaN HEMT devices is being developed to provide lower speed devices for logic and analog functions. These accomplishments position this technology for effective application to sensor interfacing, signal processing, and data communications in nuclear power plants, including operation in or near the reactor core.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2024

Output Capacitance Loss of GaN HEMTs in Steady-State Switching

The output capacitance (C OSS ) loss, a loss produced when the device’s output capacitor is charged and discharged, has become a concern for GaN high electron mobility transistors (HEMTs) in high-frequency applications. This work presents a new, easy-to-implement method for the C OSS loss characterization based on the unclamped inductive switching (UIS) setup. As compared to prior approaches, this method involves the device’s ON-state conduction and could measure the C OSS loss in a single pulse and the steady-state switching. The C OSS loss of three types of mainstream commercial GaN HEMTs is characterized, which exhibit some common dependencies including a non-monotonic relation with the dv/dt (or resonance frequency), a linear relation with the ON-state current, a power-law relation with the peak blocking voltage, and little temperature dependence. In addition, their C OSS losses all show minimal distinctions in a single pulse and the steady-state switching, despite the increased on-resistance in the steady-state switching. Furthermore, this suggests that the traps accounting for the C OSS loss possess different de-trapping time constants as compared to the traps governing the dynamic on-resistance. Finally, a unified model is established to describe the C OSS loss of all three types of GaN HEMTs. These results provide important references for the high-frequency application of GaN HEMTs and new insights into the physical origin of their C OSS loss.1

42 ENGINEERING↗
DOE OSTI2024

Temperature-induced degradation of GaN HEMT: An in situ heating study

High-power electronics, such as GaN high electron mobility transistors (HEMTs), are expected to perform reliably in high-temperature conditions. This study aims to gain an understanding of the microscopic origin of both material and device vulnerabilities to high temperatures by real-time monitoring of the onset of structural degradation under varying temperature conditions. This is achieved by operating GaN HEMT devices in situ inside a transmission electron microscope (TEM). Electron-transparent specimens are prepared from a bulk device and heated up to 800 °C. High-resolution TEM (HRTEM), scanning TEM (STEM), energy-dispersive x-ray spectroscopy (EDS), and geometric phase analysis (GPA) are performed to evaluate crystal quality, material diffusion, and strain propagation in the sample before and after heating. Gate contact area reduction is visible from 470 °C accompanied by Ni/Au intermixing near the gate/AlGaN interface. Elevated temperatures induce significant out-of-plane lattice expansion at the SiNx/GaN/AlGaN interface, as revealed by geometry-phase GPA strain maps, while in-plane strains remain relatively consistent. Exposure to temperatures exceeding 500 °C leads to almost two orders of magnitude increase in leakage current in bulk devices in this study, which complements the results from our TEM experiment. The findings of this study offer real-time visual insights into identifying the initial location of degradation and highlight the impact of temperature on the bulk device’s structure, electrical properties, and material degradation.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications

Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2020

Quantifying Dynamic On-State Resistance of GaN HEMTs for Power Converter Design via a Survey of Low and High Voltage Devices

Designing and optimizing high switching frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistances, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) switches was plagued by detrimental dynamic on-state resistance effects. This complex phenomenon for GaN devices is characterized by deviations in on-state resistance from dc operating characteristics based on design choices such as the magnitude and duration of both voltage and current stress, switching mode, and junction temperature. While device manufacturers have made improvements compared to early generation devices, experimental evidence from a survey of commercial GaN transistors highlight measurable change in on-state resistance still exists due to variations in voltage stress during hard-switching operation. After sharing insights for obtaining low noise measurements, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers. Furthermore, quantifying the performance of GaN devices with standardized metrics facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN device development.

14 SOLAR ENERGY↗
DOE OSTI2021

Analysis and Optimization of a Multi-Layer Integrated Organic Substrate for High Current GaN HEMT-Based Power Module

In this paper, analysis and optimization of a multi-layer organic substrate for high current GaN HEMT based power module are discussed. The organic multi-layer substrates can provide high electrical performance in terms of low parasitic inductance in the power loop by providing vertical layout, and shielding for reduction of common-mode noise, a common problem in fast switching power converters. Furthermore, high performance cooling solutions, such as micro-channel heat sinks, can be directly bonded to the substrate for optimum thermal management. The structure of the proposed architecture, thermal analysis and optimization of layer thickness, thermo-mechanical stress analysis of the GaN HEMT and development of a high-performance heat sink are discussed.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

True Breakdown Voltage and Overvoltage Margin of GaN Power HEMTs in Hard Switching

This work studies the dynamic breakdown voltage (BV) and overvoltage margin of a 650-V-rated commercial GaN power HEMT in hard switching. The dynamic BV measured in the hard switching circuits is over 1.4 kV, being 450 V higher than the static BV measured in the quasi-static I-V sweep. The device can survive at least 1 million hard-switching overvoltage pulses with 1.33 kV peak overvoltage (~95% dynamic BV). Recoverable device parametric shifts are observed after the 1-million pulses, featuring small reductions in threshold voltage and on-resistance. These shifts are different from the ones after the hard-switching pulses without overvoltage and are attributable to the trapping of the holes produced in impact ionization. Furthermore, these results suggest that the BV and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static BV. Index Terms— GaN, HEMT, power electronics, hard switching, breakdown voltage, overvoltage, ruggedness, reliability.

42 ENGINEERING↗
DOE OSTI2021

Kilovolt Tri-Gate GaN Junction HEMTs with High Thermal Stability

The lack of reports on the high-temperature performance of tri-gate GaN power HEMTs has raised serious concern on their competitiveness. This work demonstrates the first normally-off tri-gate GaN HEMT that can block kilovolts at 150 °C and zero gate bias. The key enabling device design is a new type of tri-gate, the junction tri-gate, which comprises p-n junction wrapping around AlGaN/GaN fins in the gate region. At 150 °C, the GaN tri-gate junction HEMT (Tri-JHEMT) retains strong gate control and stable threshold voltage, while the traditional tri-gate metal-insulator-semiconductor (MIS) HEMTs fabricated on the same wafer shows a large threshold voltage shift and inferior capabilities of voltage blocking. These results show the excellent thermal stability of GaN Tri-JHEMTs and their great potentials for power electronics applications.

Ma, Yunwei↗
DOE OSTI2024

Power Layout Design of a GaN HEMTs-Based High-Power High-Efficiency Three-Level ANPC Inverter for 800 V DC Bus System

Multiple commutation paths exist for switching devices in a three-level active neutral point clamped (3L-ANPC) inverter operation based on the selected switching state and current direction. In addition, the capacitive coupling path of the nonswitching device is a key design aspect for enabling high voltage and high current operation of gallium nitride (GaN) switches in 3L-ANPC topology. A comprehensive study of the switching transient events of inner, outer, and clamping devices of 3L-ANPC is presented in this article. The commutation mechanisms for worst-case transient voltage overshoots (TVOs) are identified. A simplified equivalent circuit model is presented to determine the design criteria for the power layout structure's parasitic inductances. A power layout strategy satisfying the design criteria is then proposed using an insulated metal substrate power printed circuit board (PCB) to enable efficient high-power operation. The proposed design minimizes the commutation and capacitive coupling path inductances to 6 nH and 11.5 nH, respectively. This enables the fast switching operation of GaN HEMTs at 800 V dc, 36 A with a low TVO of 31% verified through experimental three-level double pulse test results. Experimental evaluation of a three-phase 3L-ANPC hardware prototype based on the proposed power layout shows 99% efficiency at 800 V, 9.5 kVA and 50 kHz switching frequency. The proposed design achieves a low case-to-ambient thermal resistance of 2.3 °C/W.

42 ENGINEERING↗
DOE OSTI2020

Tri-gate GaN junction HEMT

This work presents a tri-gate GaN junction high-electron-mobility transistor (JHEMT) concept in which the p–n junction wraps around the AlGaN/GaN fins in the gate region. This tri-gate JHEMT differs from all existing GaN FinFETs and tri-gate HEMTs, as they employ a Schottky or a metal-insulator-semiconductor (MIS) gate stack. A tri-gate GaN JHEMT is fabricated using p-type NiO with the gate metal forming an Ohmic contact to NiO. The device shows minimal hysteresis and a subthreshold slope of 63 ± 2 mV/decade with an on-off current ratio of 10 8 . Compared to the tri-gate MISHEMTs fabricated on the same wafer, the tri-gate JHEMTs exhibit higher threshold voltage (V TH ) and achieve positive V TH without the need for additional AlGaN recess. In addition, this tri-gate JHEMT with a fin width of 60 nm achieves a breakdown voltage (BV) > 1500 V (defined at the drain current of 1 μA/mm at zero gate bias) and maintains the high BV with the fin length scaled down to 200 nm. In comparison, the tri-gate MISHEMTs with narrower and longer fins show punch-through at high voltages. Moreover, when compared to planar enhancement mode HEMTs, tri-gate JHEMTs show significantly lower channel sheet resistance in the gate region. Finally, these results illustrate a stronger channel depletion and electrostatic control in the junction tri-gate compared to the MIS tri-gate and suggest great promise of the tri-gate GaN JHEMTs for both high-voltage power and low-voltage power/digital applications.

36 MATERIALS SCIENCE↗
DOE OSTI2021

SiC and GaN Devices With Cryogenic Cooling

This article presents the cryogenically cooled application for wide bandgap (WBG) semiconductor devices. Characteristics of silicon carbide (SiC) and gallium nitride (GaN) at cryogenic temperatures are illustrated. SiC MOSFETs exhibit increased on-state resistance and slower switching speed at cryogenic temperatures. However, cryogenic cooling provides low ambient temperature environment and thus enables the SiC converter to operate at lower junction temperature to achieve higher efficiency compared to room temperature cooling. A cryogenically cooled MW-level SiC inverter prototype is developed and demonstrated the feasibility of operating high-power SiC converter with cryogenic cooling. GaN HEMTs exhibit more than five times on-state resistance reduction and faster switching speed at cryogenic temperatures which makes GaN HEMTs an excellent candidate for cryogenic power electronics applications. The significantly reduced on-state resistance of GaN devices provides the possibility to operate them at a current level much higher than rated current at cryogenic temperatures. A GaN double pulse test (DPT) circuit is constructed and demonstrated that GaN HEMTs can operate at nearly four times of rated current at cryogenic temperatures. Challenges of utilizing WBG device with cryogenic cooling are discussed and summarized.

42 ENGINEERING↗