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Growing of silicon nitride films, and radiation induced etch rate enhancement in silicon nitride films
Gamma, X-ray, electron, or other radiation is used to shift threshold potentials of MOS devices on logic circuits. Before irradiation MOS gates to be shifted are biased positive and other gates are grounded to substrate. Threshold lasts 10 years. Thermal annealing brings circuit back to original configuration.
FET comparator circuit detects discrete analog computer output levels without excessively loading the output amplifier of the computer. An FET common source amplifier is coupled by a differential amplifier to a bistable transistor flip-flop. This circuit provides a digital output for analog voltages above or below a predetermined level.
The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm.
The engineering development of a solid state transmitter amplifier operating in the 20 GHz frequency band using GaAs field effect transistors (FETs) was detailed. The major efforts include GaAs FET device development, single-ended amplifier stage, balanced amplifier stage, cascaded stage and radial combiner designs, and amplifier integration and test. A multistage GaAs FET amplifier capable of 8.2 W CW output over the 17.9 to 19.1 GHz frequency band was developed. The GaAs FET devices developed represent state of the art FET power device technology. Further device improvements are necessary to increase the bandwidth to 2.5 GHz, improve dc-to-RF efficiency, and increase power capability at the device level. Higher power devices will simplify the amplifier combining scheme, reducing the size and weight of the overall amplifier.
Extremely high frequency (EHF) receivers for military and NASA programs must be small, lightweight, and highly reliable. In connection with recent advances in the development of mm-wave FET devices and circuits, a basis has been obtained for the eventual replacement of diode mixer front-ends by FET preamplifiers in receivers up to 94 GHz. By placing a low noise amplifier in front of the mixer it is possible to achieve a lower system noise figure than that found in conventional mm-wave receivers. A broader bandwidth can also be provided. Attention is given to the receiver configuration, a low noise FET amplifier, an image rejection filter, a dual-gate FET mixer, a FET local oscillator, and a FET receiver.
Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.
In this DOE Early Career project “Nanoscale Ferroelectric Control of Novel Electronic States in Layered Two-Dimensional Materials,” the PI’s group has combined ferroelectric field effect with nanoscale domain imaging and writing to design the electronic and optical properties of two-dimensional (2D) van der Waals materials, including graphene and transition metal dichalcogenides MoS2 and ReS2. The van der Waals materials have been prepared into field effect transistor (FET) devices with ferroelectric gates. Through domain patterning in a ferroelectric polymer PVDF-TrEF top-gate via conductive atomic force microscopy, the team has created programmable Schottky junctions in monolayer MoS 2 , where both barrier height and I-V rectifying polarity can be reconfigured. The transport anisotropy of monolayer to few-layer ReS 2 has been mapped out by defining the entire channel into an insulating state and creating nanoscale conducting paths along different directions through domain writing in the ferroelectric top-gate. The result shows that the conductivity along and perpendicular to the Re-chain can differ by >5.5x10 4 . Theoretical modeling points to the band origin of the transport anomaly and reveals the emergence of a flat band in few-layer ReS 2 . The interfacial epitaxial relation between ReS 2 and PVDF-TrFE further promotes the formation of close-packed, highly ordered PVDF-TrFE nanowires with width of 35 nm and 10 nm. Nonvolatile modulation of quantum Hall effect has been achieved in graphene FETs with a ferroelectric oxide Ba 0.4 Sr 0.6 TiO 3 back-gate. Scattering from the remote surface optical phonon in Ba 0.4 Sr 0.6 TiO 3 limits the room temperature mobility of graphene to be about 3x10 4 cm 2 /Vs. Steep-slope switching has been achieved in MoS 2 FETs back-gated by polycrystalline Pb(Zr,Ti)O 3 , which signals a static-state negative capacitance mode without involving an additional dielectric layer. Piezoresponse force microscopy studies show that the sub-threshold swing can be well correlated with the domain wall density in Pb(Zr,Ti)O 3 . The team also observes an unconventional filtering effect of the second harmonic generation response at the MoS 2 /Pb(Zr,Ti)O 3 heterointerface, which can be accounted for by the alignment between one of the polar axes of MoS 2 and the chiral dipole rotation at the surface of domain wall in Pb(Zr,Ti)O 3 . The research supported by this DOE grant has significantly advanced the fundamental understanding and functional design of ferroelectric/2D van der Waals heterostructures for their implementation towards energy applications.
Oxide isolated islands of N and P type silicon semiconductors by epitaxial deposition and etching for complimentary MOS-FET devices
Epitaxial deposition of P-type silicon into etche grooves in N-type silicon for P-N junction for complimentary MOS-FET devices
Bandwidth, switching speed, off-state isolation, and reliability over a ten-year mission were factors in determining the optimum available technology for satellite communications switching in 1982. A proof of concept model for a 20 x 20 coupled crossbar switch matrix designed with FET devices for microwave switching and with high speed CMOS LIS for switch crosspoint addressing was fabricated and tested. Results show the design is feasible for application in a multichannel SS-TDMA communications system. Expandibility can readily be achieved with this design. A conceptual design study for a 100 x 100 switch matrix utilizing a coupled crossbar architecture implemented with a monolithic microwave integrated circuits revealed technology needs for high capacity switch matrices.
Very high performance is being developed in compound semiconductor transistors. High frequency and low noise figure operation in the GaAs FET have already been established. Substantially more performance increases are expected. A comparison of compound semiconductor materials, and their alloys, the physical concepts of high average electron velocity, and the special benefits of modulation doped heterojunction FET devices is presented.
An overview (in outline form) of cryogenically cooled, low noise microwave receivers is presented. Included are the following: (1) a state of the art summary; (2) cooled GaAs FET devices; (3) examples of cooled microwave amplifiers; (4) cooling technology; and (5) recommendations for research and development.
The development of power Field Effect Transistors (FET) operating in the 20 GHz frequency band is described. The major efforts include GaAs FET device development (both 1 W and 2 W devices), and the development of an amplifier module using these devices.
Recent testing of Enhanced Power Conversion (EPC) eGaN FET devices design for power use has shown that the devices are susceptible to Single-Event Effects (SEE) that degrade or destroy the device. The exact mechanism of the SEE is not known. The testing so far has been in the static condition, in the fully off condition, and with minimal load conditions. These conditions may not be worst case. This report presents the results of a study that tests some of the load conditions for SEE. The EPC2012 and EPC1012 were chosen for the test. The tests were performed the TAMU radiation effects facility in May and June of 2013.
This report presents the parametric characterization results of four GaN field-effect transistor (FET) devices from three manufacturers, one of which is a cascode device, and compares those results to a Si power metal-oxide-semiconductor fieldeffect transistor (MOSFET) and a SiC power MOSFET. The devices were first characterized at ambient temperature, then at cryogenic temperatures down to -196 C (LN2 temperature), and finally at ambient temperature again in the event that the device parameters were permanently affected by the cryogenic temperatures. In general, the results indicate that the GaN devices show significant improvement overall at cryogenic temperatures in the parameters characterized, such as onresistance and leakage currents, compared to the Si and SiC devices. The results show that the SiC device tested should not be used at cryogenic temperatures due to the significant increase in on-resistance. The results also show that the GaN and Si parameters characterized were either not affected by the cryogenic temperatures or changed by no more than +/-20 percent post LN2 submersion. The device that exhibited the most parametric change post LN2 submersion was the SiC power MOSFET in its leakage currents.
In this work, a comprehensive study of random spatial fluctuation of the ferroelectric (FE) phase and dielectric (DE) phase in FeFETs is conducted to understand its impact on device variation. It is found that: i) there exists a certain DE percentage threshold that below which the increase of the DE phase does not significantly impact the device memory window and variation and only above which evident device degradation can be observed; ii) increasing the DE phase increases the variation in the memory window and the coercive field distribution further exacerbates the variation, hence degrading the sensing margin; iii) decreasing the number of grains degrades the device variation, which calls for further grain size engineering for variation suppression.
Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.