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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

An integer- N frequency synthesizer for flexible on-chip clock generation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

The AMACStar ASIC for the HL-LHC ATLAS ITk Strip detector: design, verification, testing, and quality assurance

For the high-luminosity upgrade to the LHC (HL-LHC), the ATLAS detector at CERN requires an all-new inner detector, the Inner Tracker (ITk). The ITk Strip subdetector is made up of silicon modules, which include three types of radiation-hard ASICs. One of these is the Autonomous Monitor and Control (AMAC). The AMAC is manufactured by Global Foundries using 130 nm CMOS8RF DM technology and is approximately 3 by 5 mm in size. This ASIC autonomously monitors the temperatures, voltages, and currents in the module components while controlling critical values in order to prevent these quantities from reaching dangerous levels. The final design, AMACStar, was verified, tested, and ensured to perform all necessary functions. A quality control procedure using an in-house probe station set-up was developed in order to ensure that every individual chip on each wafer of AMACStars required by the ITk Strip project met performance requirements. The average per wafer yield of usable AMACStars is 92.33%, exceeding the design-specific 90% yield estimated for project costing. This estimate was based on actual yields for similar designs in this process.

Analogue electronic circuits↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
NASA NTRS2005

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Phillips, Thomas A.↗
NASA NTRS2023

Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

This poster describes a first attempt to demonstrate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Optical and SEM post-test inspections indicate fatal dielectric cracks occurred on only one of the ten SiC chips.

silicon carbide↗
NASA NTRS2004

Digital Radar-Signal Processors Implemented in FPGAs

High-performance digital electronic circuits for onboard processing of return signals in an airborne precipitation- measuring radar system have been implemented in commercially available field-programmable gate arrays (FPGAs). Previously, it was standard practice to downlink the radar-return data to a ground station for postprocessing a costly practice that prevents the nearly-real-time use of the data for automated targeting. In principle, the onboard processing could be performed by a system of about 20 personal- computer-type microprocessors; relative to such a system, the present FPGA-based processor is much smaller and consumes much less power. Alternatively, the onboard processing could be performed by an application-specific integrated circuit (ASIC), but in comparison with an ASIC implementation, the present FPGA implementation offers the advantages of (1) greater flexibility for research applications like the present one and (2) lower cost in the small production volumes typical of research applications. The generation and processing of signals in the airborne precipitation measuring radar system in question involves the following especially notable steps: The system utilizes a total of four channels two carrier frequencies and two polarizations at each frequency. The system uses pulse compression: that is, the transmitted pulse is spread out in time and the received echo of the pulse is processed with a matched filter to despread it. The return signal is band-limited and digitally demodulated to a complex baseband signal that, for each pulse, comprises a large number of samples. Each complex pair of samples (denoted a range gate in radar terminology) is associated with a numerical index that corresponds to a specific time offset from the beginning of the radar pulse, so that each such pair represents the energy reflected from a specific range. This energy and the average echo power are computed. The phase of each range bin is compared to the previous echo by complex conjugate multiplication to obtain the mean Doppler shift (and hence the mean and variance of the velocity of precipitation) of the echo at that range.

Berkun, Andrew↗
DOE OSTI2025

Microwave microscope studies of trapped vortex dynamics in superconductors

Trapped vortices in superconductors introduce residual resistance in superconducting radio-frequency (SRF) cavities and disrupt the operation of superconducting quantum and digital electronic circuits. Understanding the detailed dynamics of trapped vortices under oscillating magnetic fields is essential for advancing these technologies. We have developed a near-field magnetic microwave microscope to study the dynamics of a limited number of trapped vortices under the probe when stimulated by a localized rf magnetic field. By measuring the local second-harmonic response (𝑃 2⁢f ) at subfemto-Watt levels, we isolate signals exclusively arising from trapped vortices, excluding contributions from surface defects and Meissner screening currents. Toy models of niobium superconductor hosting vortex pinning sites are introduced and studied with time-dependent Ginzburg-Landau (TDGL) simulations of probe/sample interaction to better understand the measured second-harmonic response. The simulation results demonstrate that the second-harmonic response of trapped vortex motion under a localized rf magnetic field shares key features with the experimental data. Here, this measurement technique provides access to vortex dynamics at the micrometer scale, such as depinning events and spatially resolved pinning properties, as demonstrated in measurements on a niobium film with an antidot flux pinning array.

43 PARTICLE ACCELERATORS↗
NASA NTRS2006

Miniature Housings for Electronics With Standard Interfaces

A family of general-purpose miniature housings has been designed to contain diverse sensors, actuators, and drive circuits plus associated digital electronic readout and control circuits. The circuits contained in the housings communicate with the external world via standard RS-485 interfaces.

Howard, David E.↗
DOE OSTI2025

Event-driven readout development: testing of the EDWARD65P1 chip with integrated event generators

Building on a prototype readout integrated circuit for segmented silicon sensors with the EDWARD event-driven readout architecture, the front-end in each pixel was replaced by a hardware generator to verify readout performance, ensuring no data loss, consistent priority handling, and speed verification. Here, this generator produces Poisson-distributed readout requests with individually tunable rates per pixel via a digitally controlled oscillator. The resulting EDWARD65P1 test ASIC is a 32×32 pixel matrix with a 100 μm pitch, equipped with digital event generators simulating radiation hits at user-defined rates. Test results for this new design are presented.

47 OTHER INSTRUMENTATION↗
NASA NTRS1996

Stackable Electronic Computer Modules And Interconnections

Design concept for multiprocessor computer system calls for digital electronic processing circuits of various functionalities contained within identically shaped and sized regular polygonal modules interconnected and stacked by use of rings around edges. Rings contain wide-band bus circuits configured to provide connections to adjacent modules in same layer of stack and/or to modules in different layers. Provides flexibility of configuration to implement any of large variety of designs.

Bolotin, Gary S.↗
NASA NTRS2001

Relative Navigation for Formation Flying of Spacecraft

This paper presents a robust and efficient approach for relative navigation and attitude estimation of spacecraft flying in formation. This approach uses measurements from a new optical sensor that provides a line of sight vector from the master spacecraft to the secondary satellite. The overall system provides a novel, reliable, and autonomous relative navigation and attitude determination system, employing relatively simple electronic circuits with modest digital signal processing requirements and is fully independent of any external systems. Experimental calibration results are presented, which are used to achieve accurate line of sight measurements. State estimation for formation flying is achieved through an optimal observer design. Also, because the rotational and translational motions are coupled through the observation vectors, three approaches are suggested to separate both signals just for stability analysis. Simulation and experimental results indicate that the combined sensor/estimator approach provides accurate relative position and attitude estimates.

Alonso, Roberto↗
NASA NTRS2008

Performance of MEMS Silicon Oscillator, ASFLM1, under Wide Operating Temperature Range

Over the last few years, MEMS (Micro-Electro-Mechanical Systems) resonator-based oscillators began to be offered as commercial-off-the-shelf (COTS) parts by a few companies [1-2]. These quartz-free, miniature silicon devices could compete with the traditional crystal oscillators in providing the timing (clock function) for many digital and analog electronic circuits. They provide stable output frequency, offer great tolerance to shock and vibration, and are immune to electro-static discharge [1-2]. In addition, they are encapsulated in compact lead-free packages, cover a wide frequency range (1 MHz to 125 MHz), and are specified, depending on the grade, for extended temperature operation from -40 C to +85 C. The small size of the MEMS oscillators along with their reliability and thermal stability make them candidates for use in space exploration missions. Limited data, however, exist on the performance and reliability of these devices under operation in applications where extreme temperatures or thermal cycling swings, which are typical of space missions, are encountered. This report presents the results of the work obtained on the evaluation of an ABRACON Corporation MEMS silicon oscillator chip, type ASFLM1, under extreme temperatures.

Patterson, Richard L.↗
NASA NTRS2006

System Finds Horizontal Location of Center of Gravity

An instrumentation system rapidly and repeatedly determines the horizontal location of the center of gravity of a laboratory vehicle that slides horizontally on three air bearings (see Figure 1). Typically, knowledge of the horizontal center-of-mass location of such a vehicle is needed in order to balance the vehicle properly for an experiment and/or to assess the dynamic behavior of the vehicle. The system includes a load cell above each air bearing, electronic circuits that generate digital readings of the weight on each load cell, and a computer equipped with software that processes the readings. The total weight and, hence, the mass of the vehicle are computed from the sum of the load-cell weight readings. Then the horizontal position of the center of gravity is calculated straightforwardly as the weighted sum of the known position vectors of the air bearings, the contribution of each bearing being proportional to the weight on that bearing. In the initial application for which this system was devised, the center- of-mass calculation is particularly simple because the air bearings are located at corners of an equilateral triangle. However, the system is not restricted to this simple geometry. The system acquires and processes weight readings at a rate of 800 Hz for each load cell. The total weight and the horizontal location of the center of gravity are updated at a rate of 800/3 approx. equals 267 Hz. In a typical application, a technician would use the center-of-mass output of this instrumentation system as a guide to the manual placement of small weights on the vehicle to shift the center of gravity to a desired horizontal position. Usually, the desired horizontal position is that of the geometric center. Alternatively, this instrumentation system could be used to provide position feedback for a control system that would cause weights to be shifted automatically (see Figure 2) in an effort to keep the center of gravity at the geometric center.

Johnston, Albert S.↗
DOE OSTI2026

Advancements in NbTiN based circuits for Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

Pokhrel, A. [Imec,Heverlee,Belgium]↗