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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

White Rabbit Time Synchronization for Radiation Detector Readout Electronics

As radiation detector arrays in nuclear physics applications become larger and physically more separated, the time synchronization and trigger distribution between many channels of detector readout electronics become more challenging. Clocks and triggers are traditionally distributed through dedicated cabling, but newer methods such as the IEEE 1588 Precision Time Protocol and White Rabbit allow clock synchronization through the exchange of timing messages over Ethernet. Consequently, we report here the use of White Rabbit in a new detector readout module, the Pixie-Net XL. Herein, the White Rabbit core, data capture from multiple digitizing channels, and subsequent pulse processing for pulse height and constant fraction timing are implemented in a Kintex 7 FPGA. The detector data records include White Rabbit time stamps and are transmitted to storage through the White Rabbit core's gigabit Ethernet data path or a slower diagnostic/control link using an embedded Zynq processor. The performance is characterized by time-of-flight style measurements and by time correlation of high energy background events from cosmic showers in detectors separated by longer distances. Software for the Zynq processor can implement "software triggering", for example to limit recording of data to events where a minimum number of channels from multiple modules detect radiation at the same time.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
NASA NTRS2016

An Efficient, FPGA-Based, Cluster Detection Algorithm Implementation for a Strip Detector Readout System in a Time Projection Chamber Polarimeter

A fundamental challenge in a spaceborne application of a gas-based Time Projection Chamber (TPC) for observation of X-ray polarization is handling the large amount of data collected. The TPC polarimeter described uses the APV-25 Application Specific Integrated Circuit (ASIC) to readout a strip detector. Two dimensional photoelectron track images are created with a time projection technique and used to determine the polarization of the incident X-rays. The detector produces a 128x30 pixel image per photon interaction with each pixel registering 12 bits of collected charge. This creates challenging requirements for data storage and downlink bandwidth with only a modest incidence of photons and can have a significant impact on the overall mission cost. An approach is described for locating and isolating the photoelectron track within the detector image, yielding a much smaller data product, typically between 8x8 pixels and 20x20 pixels. This approach is implemented using a Microsemi RT-ProASIC3-3000 Field-Programmable Gate Array (FPGA), clocked at 20 MHz and utilizing 10.7k logic gates (14% of FPGA), 20 Block RAMs (17% of FPGA), and no external RAM. Results will be presented, demonstrating successful photoelectron track cluster detection with minimal impact to detector dead-time.

Polarimeter↗
DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗
NASA NTRS1990

Issues and directions in IR detector readout electronics

An introduction to the major issues encountered in the readout of imaging detector arrays in the infrared are presented. These include circuit issues such as multiplexing, buffering, and noise, as well as materials issues. Future directions in infrared readout electronics will also be discussed. These include on-chip signal processing and advanced hybridization schemes. Finally, recent work at Columbia on 2DEG-charge coupled devices for IR detector multiplexing are described.

Fossum, Eric R.↗
DOE OSTI2024

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Finally, further development of the eFPGA technology and its application to collider detector readout is discussed.

47 OTHER INSTRUMENTATION↗
NASA NTRS1997

GaAs Multiplexers for VLWIR Detector Readout Below 10 Kelvin

A multiplexer and buffer based on GaAs JFET technology is presented. This multiplexer operates normally from room temperature down to 4 Kelvin and is suitable for the readout of Very Long Wavelength Infrared Detectors that must be cooled to below 10 Kelvin.

detector arrays GaAs multiplexers↗
DOE OSTI2026

Comparing Thermal Neutron Scintillators for Use With SiPM-Readout Detectors

Scintillator-based thermal neutron detectors for scientific scattering facilities offer an effective combination of large-area coverage and good spatial resolution. At Oak Ridge National Laboratory, silicon photomultiplier (SiPM)-readout Anger cameras using 6 Li glass scintillators have been developed, but the spatial resolution of these detectors is limited by the relatively low light yield of the glass. Recently, several brighter scintillator compositions with sufficient 6 Li concentration have emerged as promising candidates for higher-resolution imaging. Here, in this work, we evaluate five scintillator materials: GS20, LiF/ZnS:Ag, LiF/ZnO:Zn, LiI:Eu, and Cs 2 LiYCl 6 :Ce, each mounted on a SiPM Anger camera. For each scintillator, the neutron detection efficiency, spatial resolution, and count rate capabilities were measured and compared. Each of the new compositions achieved a spatial resolution better than 0.5 mm, compared to 0.66 mm for GS20, with LiI:Eu reaching the best value of 0.32 mm. Although these compositions improve the spatial resolution of the Anger camera, their longer pulse decay times limit their use in high count rate applications, and the camera’s hardware must be optimized for the different properties of the new scintillators.

Neutron detectors↗
DOE OSTI2020

Evaluation & Development of Algorithms & Techniques for Streaming Detector Readout

The advancement in microelectronics capabilities, computing, and data science in the last decade has been remarkable. With the start of the 12 GeV Science Program at Jefferson Lab (JLab) and the conceptual detector design for the upcoming Ion Collider (EIC) in mind, we have evaluated and developed the possibility of evolving and improving the existing nuclear science research workflow based on these advances. Specifically, we have prototyped components of streaming readout.

43 PARTICLE ACCELERATORS↗
DOE OSTI2026

Characterization of the First Prototype of the L1K65n Differential-Output Charge-Sensitive Preamplifier ASIC for High-Performance, Low-Background HPGe Detector Readout

Next-generation neutrinoless double-beta (0νββ) decay searches require a large detector/isotope mass and very low radioactive backgrounds. The upcoming LEGEND-1000 experiment (Large Enriched Germanium Experiment for Neutrinoless double-beta Decay) constitute a ton-scale array of several hundred high-purity germanium (HPGe) detectors enriched in 76Ge, the isotope of interest. It aims to reach a sensitivity beyond 10 28 years on the 0νββ decay half-life of 76Ge, necessitating an order of magnitude reduction in background with respect to the state of the art. This will require the implementation of a dedicated application specific integrated circuit (ASIC) preamplifier that will significantly lower background contribution compared to the conventional low-mass front end (LMFE) employed in the Majorana Demonstrator and LEGEND-200 experiments while maintaining or improving energy resolution and other performance parameters. Features include a high (9 MeV) dynamic range with noise low enough to achieve a trigger threshold of <1 keV, a single power supply to reduce background-inducing cabling, and a differential output to maintain signal integrity over several meters of transmission line. The chip would be optimized to operate in liquid argon (87 K) and be able to do so reliably for ten years. Following on from an earlier 180-nm prototype, we have developed a differential-output charge-sensitive preamplifier ASIC fabricated in a 65-nm process, 1×2 mm in size, that addresses these needs. Here, we present recent results from the successful testing and characterization of the first version of this device.

ASIC↗
NASA NTRS2017

Data Reduction Pipeline for the CHARIS Integral-Field Spectrograph I: Detector Readout Calibration and Data Cube Extraction

We present the data reduction pipeline for CHARIS, a high-contrast integral-field spectrograph for the Subaru Telescope. The pipeline constructs a ramp from the raw reads using the measured nonlinear pixel response and reconstructs the data cube using one of three extraction algorithms: aperture photometry, optimal extraction, or chi-squared fitting. We measure and apply both a detector flatfield and a lenslet flatfield and reconstruct the wavelength- and position-dependent lenslet point-spread function (PSF) from images taken with a tunable laser. We use these measured PSFs to implement a chi-squared-based extraction of the data cube, with typical residuals of approximately 5 percent due to imperfect models of the under-sampled lenslet PSFs. The full two-dimensional residual of the chi-squared extraction allows us to model and remove correlated read noise, dramatically improving CHARIS's performance. The chi-squared extraction produces a data cube that has been deconvolved with the line-spread function and never performs any interpolations of either the data or the individual lenslet spectra. The extracted data cube also includes uncertainties for each spatial and spectral measurement. CHARIS's software is parallelized, written in Python and Cython, and freely available on github with a separate documentation page. Astrometric and spectrophotometric calibrations of the data cubes and PSF subtraction will be treated in a forthcoming paper.

Brandt, Timothy D.↗
DOE OSTI2025

Testing the limits of ITkPixV2: the ATLAS inner tracker pixel detector readout chip

The ITkPixV2 chip is the final production readout chip for the ATLAS Phase 2 Inner Tracker (ITk) upgrade at the upcoming High-Luminosity LHC (HL-LHC). Due to the extraordinarily high peak luminosity at the HL-LHC of 5 × 1034 cm-1 s-1, ITkPixV2 must meet significant increases in nearly all design requirements compared to the current ATLAS Inner Detector (ID), including a 10× increase in trigger rate, a 7.5× increase in hit rate, a 3× increase in radiation tolerance, and a 12.5× decrease in pixel current draw per unit area, all while maintaining a similar power per unit area as present pixel detectors. Here we present the first measurements of the ITkPixV2 chip operated at the limits of the full chip design requirements, including in particular a measurement of the activity-induced current of the chip as a function of increasing hit rate.

Le Pottier, L↗
NASA NTRS1967

Radiation detector readout system Patent

Circuit design for determining amount of photomultiplier tube light detection utilizing variable current source and dark current signals of opposite polarity

Baker, B. R.↗
NASA NTRS2011

Fast Imaging Detector Readout Circuits with In-Pixel ADCs for Fourier Transform Imaging Spectrometers

Focal plane arrays (FPAs) with high frame rates and many pixels benefit several upcoming Earth science missions including GEO-CAPE, GACM, and ACE by enabling broader spatial coverage and higher spectral resolution. FPAs for the PanFTS, a high spatial resolution Fourier transform spectrometer and a candidate instrument for the GEO-CAPE mission are the focus of the developments reported here, but this FPA technology has the potential to enable a variety of future measurements and instruments. The ESTO ACT Program funded the developed of a fast readout integrated circuit (ROIC) based on an innovative in-pixel analog-to-digital converter (ADC). The 128 X 128 pixel ROIC features 60 ?m pixels, a 14-bit ADC in each pixel and operates at a continuous frame rate of 14 kHz consuming only 1.1 W of power. The ROIC outputs digitized data completely eliminating the bulky, power consuming signal chains needed by conventional FPAs. The 128 X 128 pixel ROIC has been fabricated in CMOS and tested at the Jet Propulsion Laboratory. The current version is designed to be hybridized with PIN photodiode arrays via indium bump bonding for light detection in the visible and ultraviolet spectral regions. However, the ROIC design incorporates a small photodiode in each cell to permit detailed characterization of the ROICperformance without the need for hybridization. We will describe the essential features of the ROIC design and present results of ROIC performance measurements.

focal plane arrays (FPAs)↗
DOE OSTI2022

Conceptual design of the modular detector and readout system for the CMB-S4 survey experiment

We present the conceptual design of the modular detector and readout system for the Cosmic Microwave Background – Stage four (CMB-S4) ground-based survey experiment. CMB-S4 will map the cosmic microwave background (CMB) and the millimeter-wave sky to unprecedented sensitivity, using 500,000 superconducting detectors observing from Chile and Antarctica to map over 60% of the sky. The fundamental building block of the detector and readout system is a detector module package operated at 100 mK, which is connected to a readout and amplification chain that carries signals out to room temperature. It uses arrays of feedhorn-coupled orthomode transducers (OMT) that collect optical power from the sky onto dc-voltage-biased transition-edge sensor (TES) bolometers. The resulting current signal in the TESs is then amplified by a two-stage cryogenic Superconducting Quantum Interference Device (SQUID) system with a time-division multiplexer to reduce wire count, and matching room-temperature electronics to condition and transmit signals to the data acquisition system. Sensitivity and systematics requirements are being developed for the detector and readout system over wide range of observing bands (20 to 300 GHz) and optical powers to accomplish CMB-S4’s science goals. While the design incorporates the successes of previous generations of CMB instruments, CMB-S4 requires an order of magnitude more detectors than any prior experiment. This requires fabrication of complex superconducting circuits on over 10 m2 of silicon, as well as significant amounts of precision wiring, assembly and cryogenic testing

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2013

Fast, High-Precision Readout Circuit for Detector Arrays

The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.

Rider, David M.↗
DOE OSTI2024

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗