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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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17 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Roofline scaling trajectories: A method for parallel application and architectural performance analysis

The end of Dennard scaling signaled a shift in HPC supercomputer architectures from systems built from single-core processor architectures to systems built from multicore and eventually manycore architectures. This transition substantially complicated performance optimization and analysis as new programming models were created, new scaling methodologies deployed, and on-chip contention became a bottleneck to performance. Existing distributed memory performance models like logP and logGP were unable to capture this contention. The Roofline model was created to address this contention and its interplay with locality. However, to date, the Roofline model has focused on full-node concurrency. In this paper, we extend the Roofline model to capture the effects of concurrency on data locality and on-chip contention. We demonstrate the value of this new technique by evaluating the NAS parallel benchmarks on both multicore and manycore architectures under both strong-And weak-scaling regimes. In order to quantify the interplay between programming model and locality, we evaluate scaling under both the OpenMP and flat MPI programming models.

Ibrahim, K↗
DOE OSTI2024

Analog Computing for Science

Conventional digital computing faces fundamental physical limits: large scale computing systems already con sume tens of Megawatts of power, Dennard scaling has ended, and data movement costs dominate application performance. Next generation experimental facilities generate data at rates that overwhelm conventional pro cessing and demand real-time analysis at the source. Analog computing, which exploits the continuous dynamics of physical systems to perform computation, promises a transformative path toward orders-of-magnitude gains in energy efficiency and time-to-solution for scientific workloads.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Intelligent Sampling of Extreme-Scale Turbulence Datasets for Accurate and Efficient Spatiotemporal Model Training

With the end of Moore’s law and Dennard scaling, efficient training increasingly requires rethinking data volume. Can we train better models with significantly less data via intelligent subsampling? To explore this, we develop SICKLE, a sparse intelligent curation framework for efficient learning, featuring a novel maximum entropy (MaxEnt) sampling approach, scalable training, and energy benchmarking. We compare MaxEnt with random and phase-space sampling on large direct numerical simulation (DNS) datasets of turbulence. Evaluating SICKLE at scale on Frontier, we show that subsampling as a preprocessing step can, in many cases, improve model accuracy and substantially lower energy consumption, with observed reductions of up to 38×.

Brewer, Wes [ORNL] (ORCID:0000000236393956)↗
DOE OSTI2016

Data Movement in Data-Intensive High Performance Computing.

The cost of executing a floating point operation has been decreasing for decades at a much higher rate than that of moving data. Bandwidth and latency, two key metrics that determine the cost of moving data, have degraded significantly relative to processor cycle time and execution rate. Despite the limitation of sub-micron processor technology and the end of Dennard scaling, this trend will continue in the short-term making data movement a performance-limiting factor and an energy/power efficiency concern. Even more so in the context of large-scale and data-intensive systems and workloads. This chapter gives an overview of the aspects of moving data across a system, from the storage system to the computing system down to the node and processor level, with case study and contributions from researchers at the San Diego Supercomputer Center, the Oak Ridge National Laboratory, the Pacific Northwest National Laboratory, and the University of Delaware.

Data Movement↗
DOE OSTI2017

Piecewise empirical model (PEM) of resistive memory for pulsed analog and neuromorphic applications

With the end of Dennard scaling and the ever-increasing need for more efficient, faster computation, resistive switching devices (ReRAM), often referred to as memristors, are a promising candidate for next generation computer hardware. These devices show particular promise for use in an analog neuromorphic computing accelerator as they can be tuned to multiple states and be updated like the weights in neuromorphic algorithms. Modeling a ReRAM-based neuromorphic computing accelerator requires a compact model capable of correctly simulating the small weight update behavior associated with neuromorphic training. These small updates have a nonlinear dependence on the initial state, which has a significant impact on neural network training. Consequently, we propose an empirically derived general purpose model that can accurately capture the nonlinearity of an arbitrary two-terminal device to match pulse measurements important for neuromorphic computing applications. By defining the state of the device to be proportional to its current, the model parameters can be extracted from a series of voltages pulses that mimic the behavior of a device in an analog neuromorphic computing accelerator. This allows for a general, accurate, and intuitive compact circuit model that is applicable to different resistance switching device technologies. In this work we explain the details of the model, implement the model in the circuit simulator Xyce, and give an example of its usage to model a specific Ta/TaO x device.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Next-generation tunnel FETs: exploring material perspectives and areal tunneling configurations

The end of Dennard scaling, which facilitated proportional increases in computing power without added energy costs until the mid-2000s, has underscored the urgent need for innovative semiconductor devices that can enhance energy efficiency. Tunnel field-effect transistors (TFETs) have emerged as promising candidates to surpass the energy efficiency of conventional metal oxide semiconductor field-effect transistors (MOSFETs). Unlike MOSFETs, which rely on thermionic emission to overcome the source-channel potential barrier, TFETs operate through quantum tunneling, potentially enabling sub-60 mV dec −1 subthreshold swing (SS) for low-voltage operation. However, lateral TFETs have faced challenges in achieving adequate on-state current (I ON ) and a broad SS operation window, limiting their practical utility. This review article advocates for areal TFETs, which utilize face-to-face tunnel junctions that ideally offer step-function current turn-on characteristics and allow I ON to scale with device area rather than width. We highlight recent advancements in integrating 2D materials into tunneling structures, which could facilitate efficient band-to-band tunneling through atomically thin layers, while addressing challenges of gate field screening. We then discuss the nearer-term prospects of epitaxial areal TFETs comprising III–V compound semiconductors and group-IV semiconductors based on recent experimental progress. The review examines both quantum mechanical and semiclassical modeling approaches for TFETs, including techniques to reduce the computational complexity. The article delves into ongoing challenges in material synthesis, interface engineering, device fabrication, and integration pathways, concluding with recommendations for future research directions to overcome the fundamental power density limitations of conventional transistor technology.

2D materials↗
DOE OSTI2018

Extending Moore's Law via Computationally Error Tolerant Computing.

Dennard scaling has ended. Lowering the voltage supply (V dd ) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower V dd in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower V dd . One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. Finally, from the simulation results, this RRNS system can reduce the energy-delay-product by about 3× for multiplication intensive workloads and by about 2× in general, when compared to a non-error-correcting binary core.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs

Offloading computation from a CPU to a hardware accelerator is becoming a more common solution for improving performance because traditional gains enabled by Moore’s law and Dennard scaling have slowed. GPUs are often used as hardware accelerators, but field-programmable gate arrays (FPGAs) are gaining traction. FPGAs are beneficial because they allow hardware specific to a particular application to be created. However, they are notoriously difficult to program. To this end, two of the main FPGA manufacturers, Intel and Xilinx, have created tools and frameworks that enable the use of higher level languages to design FPGA hardware. Although Xilinx kernels can be designed by using C/C++, both Intel and Xilinx support the use of OpenCL C to architect FPGA hardware. However, not much is known about the portability and performance between these two device families other than the fact that it is theoretically possible to synthesize a kernel meant for Intel to Xilinx and vice versa.In this work, we evaluate the portability and performance of Intel and Xilinx kernels. We use OpenCL C implementations of a subset of the Rodinia benchmarking suite that were designed for an Intel FPGA and make the necessary modifications to create synthesizable OpenCL C kernels for a Xilinx FPGA. We find that the difficulty of porting certain kernel optimizations varies, depending on the construct. Once the minimum amount of modifications is made to create synthesizable hardware for the Xilinx platform, more nontrivial work is needed to improve performance. However, we find that constructs that are known to be performant for an FPGA should improve performance regardless of the platform; the difficulty comes in deciding how to invoke certain kernel optimizations while also abiding by the constraints enforced by a given platform’s hardware compiler.

Cabrera, Anthony↗
DOE OSTI2017

The Institute for Sustained Performance, Energy, and Resilience Final Project Report

Over the course of the five years of the Scientific Discovery through Advanced Computation (SciDAC-3) program, computational scientists working on behalf of the Department of Energy's Office of Science (DOE SC) exploited a new generation of petascale computing resources to make previously inaccessible discoveries in a broad range of disciplines including physics, chemistry, and materials science. The computing systems underpinning this work increased in performance potential from tens to hundreds of PFlop/s, but in the process evolving significantly from architectures in 2011, when SciDAC-3 began. Although Moore's law continues unabated, the end of Dennard scaling has necessitated a fundamental shift in computer architecture focused on power efficiency. To that end, processors are increasingly varied as they strive to satisfy performance, productivity, reliability, and energy efficiency in the face of divergent computational requirements. The diversity among these machines presents a number of challenges to merely porting today's scientific applications, much less achieving good performance. Therefore, at the beginning of SciDAC-3, USC and its collaborators anticipated that both vastly increased scale (e.g., more chips, more cores per chip, wider SIMD) and heterogeneity would exacerbate performance optimization challenges while simultaneously promoting the issues of energy and heterogeneity will exacerbate performance optimization challenges while simultaneously promoting the issues of energy consumption and resilience to the forefront. To ensure that DOE's computational scientists could successfully exploit emerging high performance computing (HPC) systems, DOE SC’s Advanced Scientific Computing Research Program (ASCR) funded the SciDAC-3 Institute for Sustained Performance, Energy, and Resilience (SUPER). Led by USC, this was a broadly based project with expertise in compilers and system tools, performance engineering, energy management, and resilience. SUPER followed the successful model developed in the previous SciDAC-2 Performance Engineering Research Institute (PERI) of leveraging the research investments DOE and others have made and integrating the results to create new capabilities beyond the reach of any one group. To accomplish this, SUPER was organized into multi-institution teams conducting the research activities in performance portability, energy efficiency, exascale resilience, and overall optimization. SUPER researchers also collaborated with other SciDAC-3 institutes, 13 of the 19 Scientific Computation Application Partnerships (SAP), as well as the broader DOE computational sciences community. These collaborations both focused our research on the real challenges facing petascale scientific computing as well as ensured the broad and immediate impact of the results of our research.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

OpenSNAPI: Toward a Unified API for SmartNICs

The end of Moore’s Law and Dennard Scaling has produced a renaissance in the field of computer architecture. Unable to continue leveraging silicon-level processor improvements to further enhance performance and scalability, system architects have been forced to explore other options. In this new era of heterogeneous architectures and hardware/software codesign, a new class of devices known as “accelerators” has emerged. Independently designed for optimized execution of distinct workloads, these devices have proven critical to the continued advancement of application performance. SmartNICs, accelerator devices integrated with a network controller, have conventionally been utilized to offload low-level networking functionality. However, newer SmartNIC variants, which incorporate a system-on-chip (SoC) with traditional designs, are challenging this precedent. Leveraging significantly augmented resources, these new devices offer increased versatility and the potential to more effectively complement a given architecture’s CPU. In this talk, we introduce the motivation underlying acceleration, explore the fundamentals of SmartNICs, and discuss traditional use cases. We also detail our initial efforts to investigate the feasibility and benefits of SmartNICs as general-purpose accelerators. We present the OpenSNAPI project created to define a uniform application programming interface (API) for this emerging class of devices. Finally, we provide a brief tutorial regarding development of SmartNIC-accelerated applications on Los Alamos National Laboratory’s SmartNIC-enabled platforms.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Artificial Intelligence-Enhanced, Multi-Level, Modular System Design

As Moore’s Law and Dennard Scaling come to an end, it is becoming increasingly important to develop non-von Neumann computing architectures that can perform low-power computing in the domains of scientific computing, artificial intelligence, embedded systems, and edge computing. Next-generation computing technologies, such as neuromorphic computing and quantum computing, have the potential to revolutionize computing. However, in order to make progress in these fields, it is necessary to fundamentally change the current computing paradigm by codesigning systems across all system level, from materials to software. Because skilled labor is limited in the field of next-generation computing, we are developing artificial intelligence-enhanced tools to automate the codesign and co-discovery of next-generation computers. Here, we develop a method called Modular and Multi-level MAchine Learning (MAMMAL) which is able to perform analog codesign and co-discovery across multiple system levels, spanning devices to circuits. We prototype MAMMAL by using it to design simple passive analog low-pass filters. We also explore methods to incorporate uncertainty quantification into MAMMAL and to accelerate MAMMAL by using emerging technologies, such as crossbar arrays. Ultimately, we believe that MAMMAL will enable rapid progress in developing next-generation computers by automating the codesign and co-discovery of electronic systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Towards Common Components and a Standard Model for Workflow Systems

The role of scalable high-performance workflows and flexible workflow management systems that can support multiple simulations will continue to increase in importance. For example, with the end of Dennard scaling, there is a need to substitute a single long running simulation with multiple repeats of shorter simulations, or concurrent replicas. Further, many scientific problems involve ensembles of simulations in order to solve a higher-level problem or produce statistically meaningful results. However most supercomputing software development and performance enhancements have focused on optimizing single- simulation performance. On the other hand, there is a strong inconsistency in the definition and practice of workflows and workflow management systems. This inconsistency often centers around the difference between several different types of workfiows, including modeling and simulation, grid, uncertainty quantification, and purely conceptual workflows. This work explores this phenomenon by examining the different types of workflows and workflow management systems, reviewing the perspective of a large supercomputing facility, examining the common features and problems of workflow management systems, and finally presenting a proposed solution based on the concept of common building blocks. The implications of the continuing proliferation of workflow management systems and the lack of interoperability between these systems are discussed from a practical perspective. In doing so, we have begun an investigation of the design and implementation of open workflow systems for supercomputers based upon common components.

Billings, Jay Jay↗
DOE OSTI2022

FastML Science Benchmarks: Accelerating Real-Time Scientific Edge Machine Learning

Applications of machine learning (ML) are growing by the day for many unique and challenging scientific applications. However, a crucial challenge facing these applications is their need for ultra low-latency and on-detector ML capabilities. Given the slowdown in Moore's law and Dennard scaling, coupled with the rapid advances in scientific instrumentation that is resulting in growing data rates, there is a need for ultra-fast ML at the extreme edge. Fast ML at the edge is essential for reducing and filtering scientific data in real-time to accelerate science experimentation and enable more profound insights. To accelerate real-time scientific edge ML hardware and software solutions, we need well-constrained benchmark tasks with enough specifications to be generically applicable and accessible. These benchmarks can guide the design of future edge ML hardware for scientific applications capable of meeting the nanosecond and microsecond level latency requirements. To this end, we present an initial set of scientific ML benchmarks, covering a variety of ML and embedded system techniques.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Computing beyond Moore's Law

Here, photolithography systems are on pace to reach atomic scale by the mid-2020s, necessitating alternatives to continue realizing faster, more predictable, and cheaper computing performance. If the end of Moore's law is real, a research agenda is needed to assess the viability of novel semiconductor technologies and navigate the ensuing challenges.

2D lithography↗
DOE OSTI2017

Architecture Independent Integrated Early Performance and Energy Estimation

The end of Dennard’s scaling, coupled to the necessity to keep increasing computational performance in constrained power envelopes, is leading developers towards the need to opti- mize applications not only for performance, but also for energy consumption. In such a scenario, solutions that enable estimating performance and energy consumption of a program as early as possible, even during development and without the necessity to access the final target hardware, can become fundamental tools to reduce the design space, the optimization effort, and provide potential opportunities to automate the optimization process itself. In this position paper, we discuss the design of a performance and energy estimation framework based on a retargetable com- piler. Our proposed approach targets the Intermediate Repre- sentation (IR) of the LLVM compiler. The IR based approach enables, after a model is built, estimation from a host different from the target architecture, even considering dynamic infor- mation. We present the rationale behind such a framework, identify opportunities and components readily available (such as the provided static analysis, quick ways to add instrumentation for dynamic profiling, and the multiple backends), and aspects that still need further research efforts (such as more effective non-linear, or machine learning based models). We also discuss a hand-developed case study, based on a simple sparse matrix vector multiplication with a linear model, to motivate the needs for such a framework.

Estimation, Compilers, Performance Analysis↗
DOE OSTI2017

It's Time to Redefine Moore's Law Again

The familiar story of Moore's law is actually inaccurate. Here, this article corrects the story, leading to different projections for the future. Moore's law is a fluid idea whose definition changes over time. It thus doesn't have the ability to "end," as is popularly reported, but merely takes different forms as the semiconductor and computer industries evolve.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Shifting Between Compute and Memory Bounds: A Compression-Enabled Roofline Model

In the evolving landscape of high-performance computing, especially to fight the end of Moore’s Law and Dennard’s Scaling, the ability to shift between compute-bound and memory-bound states is critical for enhancing adaptability and flexibility to diverse system and domain-specific architectures. Such capability is vital for optimizing performance across distinguished hardware configurations, such as accelerators, memory hierarchies, and cache systems. Despite that ad hoc optimization techniques, such as compressed/approximate computation, have been enabled for compute-/data-intensive computing for improved performance in distinct hardware settings, there lacks an understanding of 1) the rational behind performance improvement; 2) capability of different optimizations; 3) what optimization to respond to specific computational and memory demands. This work proposes a compression-enabled roofline model to facilitate this adaptability with data compression techniques to balance and transform between computational and memory demands. This model enables applications to adjust in response to the specific strengths and limitations of the underlying hardware and system to optimize resource utilization. The effectiveness of this approach is demonstrated with matrix multiplication kernels on different input sizes, with turning on/off various compression techniques, including 1) low-precision floating point; 2) sparse matrix formulation; and 3) compressed arrays with ZFP. By reducing memory transfer volumes and cache misses and increasing data locality and computational intensity through compression, the specific roofline model can transform between compute and memory bounds to align more efficiently with system capabilities. This advancement not only improves overall performance but also maximizes adaptability in diverse computing environments.

Naraparaju, Ramasoumya [University of Washington]↗