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All sourcesNASA NTRSDOE OSTI
NASA NTRS1965

Demodulation techniques for use at Goonhilly satellite-communication earth station

As part of the programme of experimental and development work to determine the optimum demodulating techniques for communication satellite systems, three types of demodulators have been investigated at the Goonhilly earth station: 1.A conventional demodulator of the type used in 960-channel telephony or television microwave radio-relay links; 2.A frequency modulation feed-back demodulator in which the deviation of the signal is reduced before it reaches the final discriminator; and 3.A variable-bandwidth 'dynamic-tracking' demodulator in which the resonant frequency of a narrow bandwidth tuned circuit is moved rapidly to follow the nominal instantaneous frequency of the incoming signal. The conventional demodulator will not be discussed in detail here;. however, information is given on two specialized demodulators.

COMMUNICATIONS SATELLITE↗
NASA NTRS1982

Demodulation of PPM for Reed-Solomon coded optical space channel

The paper proposes a delta-max demodulator for Reed-Solomon coded M-ary PPM modulation over optical (laser) channels including satellite-to-satellite and deep-space-vehicle-to-relay-satellite communications. This demodulator is compared with the threshold demodulator currently in use, and the two demodulators are shown to have identical performance in the absence of background noise. The delta-max demodulator is found to outperform the threshold demodulator as the intensity of background noise increases.

Divsalar, D.↗
NASA NTRS1988

Digital carrier demodulation for the DSN Advanced Receiver

The digital in-phase and quadrature (I and Q) carrier demodulation for the Deep Space Network's (DSN) Advanced Receiver is described and analyzed. The system provides coherent demodulation for a variety of modulation formats including Binary Phase Shift Keying (BPSK), BPSK with a carrier residual, Quadrature Phase Shift Keying (QPSK), Offset-QPSK (OQPSK), and Minimum Shift Keying (MSK). The focus is on the theory and hardware design of the halfband filters which are the integral part of the demodulator. The underlying theory of the filters is summarized, a breadboard hardware design is described, and a VLSI implementation is proposed which significantly decreases the hardware. A second important problem analyzed is DC-offset in the demodulator. This is a serious problem which translates into bias error in the residual carrier phase detector. The dynamic range of the complex mixer is analyzed using a probabilistic approach. It is deduced that the resulting static phase error is less than 0.2 deg when the ratio of carrier power to noise power in the demodulator input bandwidth is -72 dB or higher. Thus, the static phase error is negligible at a carrier power to noise spectral density of 0 dB-Hz for a 15 MHz bandwidth demodulator.

Sadr, R.↗
NASA NTRS1993

Digital receiver for on-board FM/FSK-FM/BPSK demodulation

An all-digital demodulator FM/FSK-FM/BPSK is presented. The proposed architecture allows the 1-bit IF down-sampling technique with the hardware simplification of receiver analog section. The receiver exhibits great flexibility both in terms of signal demodulation (FSK or BPSK, subcarrier/ tone frequency, data rate) and interface capability. The demodulator is going to be realized in a VLSI chip (20 Kgate complexity). This paper describes the demodulator structure and its demodulation performances obtained with a breadboard based on programmable logic devices. The choice of a simple and effective scheme for frequency detection (FM and FSK demodulators) is suggested by system design considerations as well. Signal processing algorithms include also a Costas carrier phase recovery scheme in the case of BPSK signal and data transition tracking loop for the bit clock recovery. Test results address this solution as one of the most suitable for TT&C space application.

Boscagli, G.↗
NASA NTRS1993

Performance of the unique-word-reverse-modulation type demodulator for mobile satellite communications

This paper proposes a new type of coherent demodulator, the unique-word (UW)-reverse-modulation type demodulator, for burst signal controlled by voice operated transmitter (VOX) in mobile satellite communication channels. The demodulator has three individual circuits: a pre-detection signal combiner, a pre-detection UW detector, and a UW-reverse-modulation type demodulator. The pre-detection signal combiner combines signal sequences received by two antennas and improves bit energy-to-noise power density ratio (E(sub b)/N(sub 0)) 2.5 dB to yield 10(exp -3) average bit error rate (BER) when carrier power-to-multipath power ratio (CMR) is 15 dB. The pre-detection UW detector improves UW detection probability when the frequency offset is large. The UW-reverse-modulation type demodulator realizes a maximum pull-in frequency of 3.9 kHz, the pull-in time is 2.4 seconds and frequency error is less than 20 Hz. The performances of this demodulator are confirmed through computer simulations and its effect is clarified in real-time experiments at a bit rate of 16.8 kbps using a digital signal processor (DSP).

Dohi, Tomohiro↗
NASA NTRS1975

On optimal soft-decision demodulation

Wozencraft and Kennedy have suggested that the appropriate demodulator criterion of goodness is the cut-off rate of the discrete memoryless channel created by the modulation system; the criterion of goodness adopted in this note is the symmetric cut-off rate which differs from the former criterion only in that the signals are assumed equally likely. Massey's necessary condition for optimal demodulation of binary signals is generalized to M-ary signals. It is shown that the optimal demodulator decision regions in likelihood space are bounded by hyperplanes. An iterative method is formulated for finding these optimal decision regions from an initial good quess. For additive white Gaussian noise, the corresponding optimal decision regions in signal space are bounded by hypersurfaces with hyperplane asymptotes; these asymptotes themselves bound the decision regions of a demodulator which, in several examples, is shown to be virtually optimal. In many cases, the necessary condition for demodulator optimality is also sufficient, but a counter example to its general sufficiency is given.

Lee, L. N.↗
NASA NTRS1993

Multichannel demultiplexer-demodulator

One of the critical satellite technologies in a meshed VSAT (very small aperture terminal) satellite communication networks utilizing FDMA (frequency division multiple access) uplinks is a multichannel demultiplexer/demodulator (MCDD). TRW Electronic Systems Group developed a proof-of-concept (POC) MCDD using advanced digital technologies. This POC model demonstrates the capability of demultiplexing and demodulating multiple low to medium data rate FDMA uplinks with potential for expansion to demultiplexing and demodulating hundreds to thousands of narrowband uplinks. The TRW approach uses baseband sampling followed by successive wideband and narrowband channelizers with each channelizer feeding into a multirate, time-shared demodulator. A full-scale MCDD would consist of an 8 bit A/D sampling at 92.16 MHz, four wideband channelizers capable of demultiplexing eight wideband channels, thirty-two narrowband channelizers capable of demultiplexing one wideband signal into 32 narrowband channels, and thirty-two multirate demodulators. The POC model consists of an 8 bit A/D sampling at 23.04 MHz, one wideband channelizer, 16 narrowband channelizers, and three multirate demodulators. The implementation loss of the wideband and narrowband channels is 0.3dB and 0.75dB at 10(exp -7) E(sub b)/N(sub o) respectively.

Courtois, Hector↗
NASA NTRS1998

High Rate Digital Demodulator ASIC

The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

Ghuman, Parminder↗
NASA NTRS2001

Method and Apparatus for High Data Rate Demodulation

A method to demodulate BPSK or QPSK data using clock rates for the receiver demodulator of one-fourth the data rate is presented. This is accomplished through multirate digital signal processing techniques. The data is sampled with an analog-to-digital converter and then converted from a serial data stream to a parallel data stream. This signal processing requires a clock cycle four times the data rate. Once converted into a parallel data stream, the demodulation operations including complex baseband mixing, lowpass filtering, detection filtering, symbol-timing recovery, and carrier recovery are all accomplished at a rate one-fourth the data rate. The clock cycle required is one-sixteenth that required by a traditional serial receiver based on straight convolution. The high rate data demodulator will demodulate BPSK, QPSK, UQPSK, and DQPSK with data rates ranging from 10 Mega-symbols to more than 300 Mega-symbols per second. This method requires less clock cycles per symbol tan traditional serial convolution techniques.

Gerald J Grebowsky↗
NASA NTRS1982

PPM demodulation for Reed-Solomon decoding for the optical space channel

The use of Reed-Solomon (RS) block codes over the pulse position modulated (PPM) frames to obtain the largest degree of error correction is considered. Since RS codes can correct both symbol errors and symbol erasures, a question arises as to the best way to demodulate the PPM laser fields in order to generate the input symbols for the RS decoder. The method selected for demodulating (converting the received laser field to digital symbols) defines the erasure and transmitted symbols of the laser link, and therefore determines the work error probabilities of the system. Several demodulating schemes are considered, and the effect of each on RS decoding performance computed. This computation was carried out for various optical receiver models. It is shown that simple threshold decisioning of pulse slots produces performance that degrades as the background noise increases. This is caused by the generation of too many erasures for the RS decoder to handle. A decision scheme, delta-max demodulation which offers improvement over threshold decisioning by redefining the generation of an erasure is proposed.

Divsalar, D.↗
NASA NTRS1989

A coherent digital demodulator for multiple signal formats and widely varying data rates

The Tracking and Data Relay Satellite System (TDRSS) uses four ground station demodulators for K-band signals with data rates from 1 kb/s to 300 Mb/s. The author discusses the feasibility of replacing these demodulators with a single digital demodulator that may be reconfigured by altering stored parameters to accommodate all signal formats and data rates. This implementation will reduce total ground station cost and facilitate automation of ground station operation. Analysis of system performance concentrates on the carrier tracking loop. Analytic and simulation results relate system performance to parameter values and signal format as data rate and power vary independently on the In-phase and quadrature channels. It is demonstrated that a single digital demodulator can support TDRSS-compatible signals at data rates conservatively extending from 1K symbols/s to 10M symbols/s, using off-the-shelf hardware with 6 or more bits of accuracy.

Mcguffin, Bruce F.↗
NASA NTRS1991

A parallel-pipelined architecture for a multi carrier demodulator

Analog devices have been used for processing the information on board the satellites. Presently, digital devices are being used because they are economical and flexible as compared to their analog counterparts. Several schemes of digital transmission can be used depending on the data rate requirement of the user. An economical scheme of transmission for small earth stations uses single channel per carrier/frequency division multiple access (SCPC/FDMA) on the uplink and time division multiplexing (TDM) on the downlink. This is a typical communication service offered to low data rate users in commercial mass market. These channels usually pertain to either voice or data transmission. An efficient digital demodulator architecture is provided for a large number of law data rate users. A demodulator primarily consists of carrier, clock, and data recovery modules. This design uses principles of parallel processing, pipelining, and time sharing schemes to process large numbers of voice or data channels. It maintains the optimum throughput which is derived from the designed architecture and from the use of high speed components. The design is optimized for reduced power and area requirements. This is essential for satellite applications. The design is also flexible in processing a group of a varying number of channels. The algorithms that are used are verified by the use of a computer aided software engineering (CASE) tool called the Block Oriented System Simulator. The data flow, control circuitry, and interface of the hardware design is simulated in C language. Also, a multiprocessor approach is provided to map, model, and simulate the demodulation algorithms mainly from a speed view point. A hypercude based architecture implementation is provided for such a scheme of operation. The hypercube structure and the demodulation models on hypercubes are simulated in Ada.

Kwatra, S. C.↗
NASA NTRS1995

Pseudocoherent Demodulation Of DPSK Radio Signals

Three schemes for pseudocoherent demodulation of differential-phase-shift keyed (DPSK) radio signals proposed for use in land-mobile/satellite communications. Enables fast reacquisition. Also amounts to compromise between two extremes of coherent demodulation and differentially coherent demodulation, for which bit-error rates greater than those of coherent demodulation by amounts corresponding to difference of about 1 dB in bit-energy/noise-energy ratio. Based on maximum-likelihood estimation and detection during N-symbol observation periods, where N integer typically chosen between 5 and 15.

Divsalar, Dariush↗
NASA NTRS1975

Performance of quasi-optimum digital FM demodulators for fading channels

This paper deals with the problem of digital demodulation of FM signals transmitted over Rayleigh and Rician fading channels. The Rayleigh and Rician fading channels are represented by two quadrature multiplicative nonzero mean white Gaussian processes in addition to an additive zero-mean white Gaussian noise. Quasi-optimum digital baseband demodulation algorithms using various nonlinear estimation techniques are derived. The digital demodulator structures are then simulated on a digital computer for an FM system with first order message spectrum for various values of the parameters for Rayleigh and Rician channels.

Dharamsi, M. T.↗
NASA NTRS1976

On optimal soft-decision demodulation

A necessary condition is derived for optimal J-ary coherent demodulation of M-ary (M greater than 2) signals. Optimality is defined as maximality of the symmetric cutoff rate of the resulting discrete memoryless channel. Using a counterexample, it is shown that the condition derived is generally not sufficient for optimality. This condition is employed as the basis for an iterative optimization method to find the optimal demodulator decision regions from an initial 'good guess'. In general, these regions are found to be bounded by hyperplanes in likelihood space; the corresponding regions in signal space are found to have hyperplane asymptotes for the important case of additive white Gaussian noise. Some examples are presented, showing that the regions in signal space bounded by these asymptotic hyperplanes define demodulator decision regions that are virtually optimal.

Lee, L.-N.↗
NASA NTRS1979

Digital PSK to BiO-L demodulator for 2 sup nx(bit rate) carrier

A phase shift key (PSK) to BiO-L demodulator which uses standard digital integrated circuits is discussed. The demodulator produces NRZ-L, bit clock, and BiO-L outputs from digital PSK input signals for which the carrier is a 2 to the Nth multiple of the bit rate. Various bit and carrier rates which are accommodated by changing various component values within the demodulator are described. The use of the unit for sinusoidal inputs as well as digital inputs is discussed.

Shull, T. A.↗
NASA NTRS1982

A PPM modulator and demodulator for the 2.5 bit/detected photon demonstration

In addition to performing the basic pulse position modulation and demodulation, the hardware described also indicates the occurrence of erasures and errors of various types. The analyzer portion of the circuit counts the number of pulses received in a word, demodulates a second input pulse (if one is received), indicates the occurrence of erasures, and detects PPM word errors. Word errors are detected by comparing the modulator input word to the corresponding demodulator output. These functions are provided mainly for testing and diagnosis of the system during the feasibility demonstration period.

Marshall, W. K.↗
NASA NTRS1982

Digital demodulator

A digital demodulator for converting pulse code modulated data from phase shift key (PSK) to non return to zero (NRZ) and to biphase data is described. The demodulator is composed of standard integrated logic circuits. The key to the demodulation function is a pair of cross coupled one shot multivibrators and which with a flip-flop produce the NRZ-L is all that is required, the circuitry is greatly simplified and the 2(v) times bit rate contraint can be removed from the carrier. A flip-flop, an OR gate, and AND gate and a binary counter generate the bit rate clock (BTCK) for the NRZ-L. The remainder of the circuitry is for converting the NRZ-L and BTCK into biphase data. The device was designed for use in the space shuttle bay environment measurements.

Shull, T. A.↗