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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2012

Hands-on Performance Tuning of 3D Finite Difference Earthquake Simulation on GPU Fermi Chipset

3D simulation of earthquake ground motion is one of the most challenging computational problems in science. The emergence of graphic processing units (GPU) as an effective alternative to traditional general purpose processors has become increasingly capable in terms of accelerating scientific computing research. In this paper, we describe our experiences in porting AWP-ODC, a 3D finite difference seismic wave propagation code, to the latest GPU Fermi chipset. We completely rewrote this Fortran-based 13-point asymmetric stencil computation code in C and MPI-CUDA in order to take advantage of the powerful GPU computing capabilities. Our new CUDA code implemented the asymmetric 3D stencil on Fermi to make the best use of GPU on-chip memory for an aggressive parallel efficiency. Benchmark on NVIDIA Tesla M2090 demonstrated 10x speedup versus the original fully optimized AWP-ODC FORTRAN MPI code running on a single Intel Nehalem 2.4 GHz CPU socket (4 cores/CPU), and 15x speedup versus the same MPI code running on a single AMD Istanbul 2.6 GHz CPU socket (6 cores/CPU). Sustained single-GPU performance of 143.8 GFLOPS in single precision is benchmarked for the testing case of 128x128x960 mesh size.

3D Stencil Computation↗
NASA NTRS1990

NASA Langley and AF RADC high-speed fiber optic transceiver program

NASA-Langley and the USAF Rome Air Development Center have been pursuing the development of military- and space-qualified fiber optic transceivers for a variety of ground-based, space-based, and general avionic applications. An initial development pursued a design called the multipurpose fiber optic transceiver (MFOX) and provided a family of fiber optic transceivers which operated up to 1 Gb/s. Currently, a second generation of high-speed fiber optic transceivers (HSFOX) is being developed. This design will utilize an all-integrated-circuits approach in order to develop a lighter-weight, smaller-size, and more efficient transceiver. The high-speed fiber optic transceiver will be military-and-space-operating in the 0.05-5 Gb/s data rate range. The initial results of tests, performance, and availability of commercial high-speed all-integrated-circuit chipsets for fiber-optic transceivers are discussed, as well as the performance of transceivers fabricated from these chipsets.

Hendricks, Herbert D.↗
NASA NTRS1993

Radiation hardened microprocessor for small payloads

The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

Shah, Ravi↗
NASA NTRS2001

Status of the Direct Data Distribution (D(exp 3)) Experiment

NASA Glenn Research Center's Direct Data Distribution (D3) project will demonstrate an advanced, high-performance communications system that transmits information from an advanced technology payload carried by a NASA spacecraft in low Earth orbit (LEO) to a small receiving terminal on Earth. The space-based communications package will utilize a solid-state, K-band phased-array antenna that electronically steers the radiated energy beam toward a low-cost, tracking ground terminal, thereby providing agile, vibration-free, electronic steering at reduced size and weight with increased reliability. The array-based link will also demonstrate new digital processing technology that will allow the transmission of substantially increased amounts of latency-tolerant data collected from the LEO spacecraft directly to NASA field centers, principal investigators, or into the commercial terrestrial communications network. The technologies demonstrated by D3 will facilitate NASA's transition from using Government-owned communication assets to using commercial communication services. The hardware for D3 will incorporate advanced technology components developed under the High Rate Data Delivery (HRDD) Thrust Area of NASA's Office of Aerospace Technology Space Base Program at Glenn's Communications Technology Division. The flight segment components will include the electrically steerable phased-array antenna, which is being built by the Raytheon System Corporation and utilizes monolithic microwave integrated circuit (MMIC) technology operating at 19.05 GHz; and the digital encoder/modulator chipset, which uses four-channel orthogonal frequency division multiplexing (OFDM). The encoder/modulator will use a chipset developed by SICOM, Inc., which is both bandwidth and power efficient. The ground segment components will include a low-cost, open-loop tracking ground terminal incorporating a cryoreceiver to minimize terminal size without compromising receiver capability. The project is planning to hold a critical design review in the second quarter of fiscal year 2002.

Wald, Lawrence↗
DOE OSTI2018

Performance evaluation of the three-point angular correlation function

In recent years, we have observed an increase in the diversity of the processors ecosystem. Different designs and architectures are being studied based on their performance and power characteristics. While using benchmarks for this purpose allows for reproducibility and easy understanding of the results, using real scientific applications allows researchers to realize the actual implications of each design on the overall performance of their codes. This paper analyzes the performance of different implementations of a three-point angular correlation function. This function is used in the study of Large-Scale Distribution of galaxies in a variety of computational platforms. The function is based on histogram construction and presents a large computational cost. This cost dramatically increases with the size of the datasets. We have considered two different GPUs, a set of x86 Intel machines (multi- and many-core), ARM chipsets, as well as an FPGA. We first study the best possible implementation for each platform in terms of time to solution. We then compare the power used by those platforms for a predefined number of datasets. Energy is one of the main constraints that computer architects are facing nowadays. The results will be used to evaluate the performance of this function considering those two targets – time and energy – for those platforms and to analyze the suitability of each of those platforms for this specific problem.

Computer Science↗
DOE OSTI2016

ALICE inner tracking system readout electronics prototype testing with the CERN "Giga Bit Transceiver''

The ALICE Collaboration is preparing a major detector upgrade for the LHC Run 3, which includes the construction of a new silicon pixel based Inner Tracking System (ITS). The ITS readout system consists of 192 readout boards to control the sensors and their power system, receive triggers, and deliver sensor data to the DAQ. To prototype various aspects of this readout system, an FPGA based carrier board and an associated FMC daughter card containing the CERN Gigabit Transceiver (GBT) chipset have been developed. Furthermore, this contribution describes laboratory and radiation testing results with this prototype board set.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Evaluating Modern GPU Interconnect: PCIe, NVLink, NV-SLI, NVSwitch and GPUDirect

High performance multi-GPU computing becomes an inevitable trend due to the ever-increasing demand on computation capability in emerging domains such as deep learning, big data and planet-scale simulations. However, the lack of deep understanding on how modern GPUs can be connected and the real impact of state-of-the-art interconnect technology on multi-GPU application performance become a hurdle. In this paper, we fill the gap by conducting a thorough evaluation on five latest types of modern GPU interconnects: PCIe, NVLink-V1, NVLink-V2, NVLink-SLI and NVSwitch, from six high-end servers and HPC platforms: NVIDIA P100-DGX-1, V100-DGX-1, DGX-2, OLCF’s SummitDev and Summit supercomputers, as well as an SLI-linked system with two NVIDIA Turing RTX-2080 GPUs. Based on the empirical evaluation, we have observed four new types of GPU communication network NUMA effects: three are triggered by NVLink’s topology, connectivity and routing, while one is caused by PCIe chipset design issue. These observations indicate that, for a multi-GPU application running in a multi-GPU node, choosing the right GPU combination can impose considerable impact on GPU communication efficiency, as well as an application’s overall performance. Our evaluation can be leveraged in building practical multi-GPU performance models, which are vital for GPU task allocation, scheduling and migration in a shared environment (e.g., AI cloud and HPC centers), as well as communication-oriented performance tuning.

Performance Evaluation, GPU, Interconnect, NUMA, P↗
NASA NTRS1993

A high-speed lossless data compression system for space applications

This paper reports on the integration of a lossless data compression/decompression chipset into a space data system architecture. For its compression engine, the data system incorporates the Universal Source Encoder (USE) designed for the NASA/Goddard Space Flight Center. Currently, the data compression testbed generates video frames consisting of 512 lines of 512 pixels having 8-bit resolution. Each image is passed through the USE where the lines are internally partitioned into 16-word blocks. These blocks are adaptively encoded across widely varying entropy levels using a Rice 12-option set coding algorithm. The current system operates at an Input/Output rate of 10 Msamples/s or 80 Mbits/s for each buffered input line. Frame and line synchronization for each image are maintained through the use of uniquely decodable command words. Length information of each variable length compressed image line is also included in the output stream. The data and command information are passed to the next stage of the system architecture through a serial fiber-optic transmitter. The initial segment of this stage consists of packetizer hardware which adds an appropriate CCSDS header to the received source data. An uncompressed mode is optionally available to pass image lines directly to the packetizer hardware. A data decompression testbed has also been developed to confirm the data compression operation.

Miko, Joe↗
NASA NTRS2001

Flight Performance Evaluation of Three GPS Receivers for Sounding Rocket Tracking

In preparation for the European Space Agency Maxus-4 mission, a sounding rocket test flight was carried out at Esrange,, near Kiruna, Sweden on February 19, 2001 to validate existing ground facilities and range safety installations. Due to the absence of a dedicated scientific payload, the flight offered the opportunity to test multiple GPS receivers and assess their performance for the tracking of sounding rockets. The receivers included an Ashtech G12 HDMA receiver, a BAE (Canadian Marconi) Allstar receiver and a Mitel Orion receiver. All of them provide CIA code tracking on the L1 frequency to determine the user position and make use of Doppler measurements to derive the instantaneous velocity. Among the receivers, the G12 has been optimized for use under highly dynamic conditions and has earlier been flown successfully on NASA sounding rockets [Bull, ION-GPS-2000]. The Allstar is representative of common single frequency receivers for terrestrial applications and received no particular modification, except for the disabling of the common altitude and velocity constraints that would otherwise inhibit its use for space application. The Orion receiver, finally, employs the same Mitel chipset as the Allstar, but has received various firmware modifications by DLR to safeguard it against signal losses and improve its tracking performance [Montenbruck et al., ION-GPS-2000]. While the two NASA receivers were driven by a common wrap-around antenna, the DLR experiment made use of a switchable antenna system comprising a helical antenna in the tip of the rocket and two blade antennas attached to the body of the vehicle. During the boost a peak acceleration of roughly 17g's was achieved which resulted in a velocity of about 1100 m/s at the end of the burn. At apogee, the rocket reached a maximum altitude of over 80 km. A detailed analysis of the attained flight data will be given in the paper together with a evaluation of different receiver designs and antenna concepts.

Bull, Barton↗
NASA NTRS2002

Flight Performance Evaluation of Three GPS Receivers for Sounding Rocket Tracking

In preparation for the European Space Agency Maxus-4 mission, a sounding rocket test flight was carried out at Esrange, near Kiruna, Sweden on February 19, 2001 to validate existing ground facilities and range safety installations. Due to the absence of a dedicated scientific payload, the flight offered the opportunity to test multiple GPS receivers and assess their performance for the tracking of sounding rockets. The receivers included an Ashtech G12 HDMA receiver, a BAE (Canadian Marconi) Allstar receiver and a Mitel Orion receiver. All of them provide C/A code tracking on the L1 frequency to determine the user position and make use of Doppler measurements to derive the instantaneous velocity. Among the receivers, the G12 has been optimized for use under highly dynamic conditions and has earlier been flown successfully on NASA sounding rockets. The Allstar is representative of common single frequency receivers for terrestrial applications and received no particular modification, except for the disabling of the common altitude and velocity constraints that would otherwise inhibit its use for space application. The Orion receiver, finally, employs the same Mitel chipset as the Allstar, but has received various firmware modifications by DLR to safeguard it against signal losses and improve its tracking performance. While the two NASA receivers were driven by a common wrap-around antenna, the DLR experiment made use of a switchable antenna system comprising a helical antenna in the tip of the rocket and two blade antennas attached to the body of the vehicle. During the boost a peak acceleration of roughly l7g's was achieved which resulted in a velocity of about 1100 m/s at the end of the burn. At apogee, the rocket reached an altitude of over 80 km. A detailed analysis of the attained flight data is given together with a evaluation of different receiver designs and antenna concepts.

Bull, Barton↗
NASA NTRS2009

Software Configurable Multichannel Transceiver

Emerging test instrumentation and test scenarios increasingly require network communication to manage complexity. Adapting wireless communication infrastructure to accommodate challenging testing needs can benefit from reconfigurable radio technology. A fundamental requirement for a software-definable radio system is independence from carrier frequencies, one of the radio components that to date has seen only limited progress toward programmability. This paper overviews an ongoing project to validate the viability of a promising chipset that performs conversion of radio frequency (RF) signals directly into digital data for the wireless receiver and, for the transmitter, converts digital data into RF signals. The Software Configurable Multichannel Transceiver (SCMT) enables four transmitters and four receivers in a single unit the size of a commodity disk drive, programmable for any frequency band between 1 MHz and 6 GHz.

Freudinger, Lawrence C.↗
NASA NTRS2009

Frequency Agile Transceiver for Advanced Vehicle Data Links

Emerging and next-generation test instrumentation increasingly relies on network communication to manage complex and dynamic test scenarios, particularly for uninhabited autonomous systems. Adapting wireless communication infrastructure to accommodate challenging testing needs can benefit from reconfigurable radio technology. Frequency agility is one characteristic of reconfigurable radios that to date has seen only limited progress toward programmability. This paper overviews an ongoing project to validate a promising chipset that performs conversion of RF signals directly into digital data for the wireless receiver and, for the transmitter, converts digital data into RF signals. The Software Configurable Multichannel Transceiver (SCMT) enables four transmitters and four receivers in a single unit, programmable for any frequency band between 1 MHz and 6 GHz.

Freudinger, Lawrence C.↗
NASA NTRS2007

Two-Way Communication Using RFID Equipment and Techniques

Equipment and techniques used in radio-frequency identification (RFID) would be extended, according to a proposal, to enable short-range, two-way communication between electronic products and host computers. In one example of a typical contemplated application, the purpose of the short-range radio communication would be to transfer image data from a user s digital still or video camera to the user s computer for recording and/or processing. The concept is also applicable to consumer electronic products other than digital cameras (for example, cellular telephones, portable computers, or motion sensors in alarm systems), and to a variety of industrial and scientific sensors and other devices that generate data. Until now, RFID has been used to exchange small amounts of mostly static information for identifying and tracking assets. Information pertaining to an asset (typically, an object in inventory to be tracked) is contained in miniature electronic circuitry in an RFID tag attached to the object. Conventional RFID equipment and techniques enable a host computer to read data from and, in some cases, to write data to, RFID tags, but they do not enable such additional functions as sending commands to, or retrieving possibly large quantities of dynamic data from, RFID-tagged devices. The proposal would enable such additional functions. The figure schematically depicts an implementation of the proposal for a sensory device (e.g., a digital camera) that includes circuitry that converts sensory information to digital data. In addition to the basic sensory device, there would be a controller and a memory that would store the sensor data and/or data from the controller. The device would also be equipped with a conventional RFID chipset and antenna, which would communicate with a host computer via an RFID reader. The controller would function partly as a communication interface, implementing two-way communication protocols at all levels (including RFID if needed) between the sensory device and the memory and between the host computer and the memory. The controller would perform power V

Jedry, Thomas↗
NASA NTRS2021

Lunar Asset Messaging and On Orbit Navigation

NASA has titled its 2020 thrust for the Moon, Artemis. The increased focus on the Moon as a destination for future human and robotic expeditions necessitates general purpose navigational and communications infrastructure reducing their complexity to help establish a sustained presence. A framework through which Lunar missions can relay communications and localize their positions shifts the burden from the individual mission and enables resource allocation tailored to mission-specific goals. During the summer of 2020, student interns under the Innovation to Flight (i2F) program at the National Aeronautics and Space Administration’s (NASA) Jet Propulsion Laboratory (JPL) in collaboration with the University of Colorado Boulder designed, built, and tested a prototype framework capable of providing surface assets with communication and positioning services. The team utilized the existing i2F CubeSat bus in addition to developing several CubeSat engineering development units (EDUs), a ground vehicle, and a ground station to simulate a scenario in which a lunar surface mission is supported by these services. A primary goal of the summer was to develop a method for localizing the ground vehicle through trilateration. Distances are inferred from the round-trip time of flight (ToF) of radio signals between an asset and several elements. Signals were sent and received using LimeSDR software defined radios on-board both the ground vehicle and the EDUs; ToF and trilateration were calculated on a Qualcomm Snapdragon development board located within the LA MOON payload data system. The ModalAI chipset on the Qualcomm was instrumental in executing visual based position estimation. Communications was facilitated through a bent-pipe approach addressing the NASA requirement to provide solutions for in communication denied locations. The ground vehicle relayed information to other surface assets in addition to its ground station through the supporting constellation. This project demonstrates the feasibility of a lunar CubeSat constellation for the support of surface assets and explores packaging and operations of the components critical to trilateration and bent-pipe communication into a standard CubeSat form factor. When implemented, this framework will open a door for new surface missions designed with lower power requirements and increased operational access.

Huang, Calvin↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗