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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1980

Critique of the Hughes Aircraft shuttle Ku band leading edge bit synchronizer

A bit synchronizer is analyzed via timing diagrams in a noise-free environment. It is believed that this new bit synchronizer will track the rising edge of the data bits with 25% asymmetry and up to a 90 deg phase shift between the received clock and data bit timing. In addition, the data bits will be demodulated correctly. It is not true that phase shifts larger than 90 deg will necessarily be corrected by this bit synchronizer. However, the specifications currently require the loop to operate over only a + or - 75 deg phase shift between the received data stream leading edges and the bit synchronizer leading edges; consequently, there should be no problem.

Holmes, J. K.↗
NASA NTRS1979

Multiple speed expandable bit synchronizer

A multiple speed bit synchronizer was designed for installation in an inertial navigation system data decoder to extract non-return-to-zero level data and clock signal from biphase level data. The circuit automatically senses one of four pre-determined biphase data rates and synchronizes the proper clock rate to the data. Through a simple expansion of the basic design, synchronization of more than four binarily related data rates can be accomplished. The design provides an easily adaptable, low cost, low power alternative to external bit synchronizers with additional savings in size and weight.

Bundinger, J. M.↗
NASA NTRS1989

Single chip fixed frequency bit synchronizer

A single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device is described. The bit synchronizer is modeled after a digital transition tracking loop for symbol estimation and employs a first-order incremental phase modulator for closed-loop symbol synchronization. The BER and tracking performance is modeled and compared to optimum designs. The bit synchronizer was developed for the Space Shuttle.

Butler, Madeline J.↗
NASA NTRS1985

Bit synchronization of differentially detected MSK and GMSK

The filter-square bit synchronizer has been previously proposed and shown to give near optimum performance for coherent PSK systems. In this paper, the same bit synchronization scheme is analyzed for a differentially detected GMSK system. It is shown that the filter-square bit synchronizer can successfully work in a differential phase detection receiver. By making linear approximations appropriate for high loop signal-to-noise ratio operation (the usual case of interest in tracking), it is demonstrated that the mean-square bit sync jitter of differentially detected GMSK system reveals striking similarities both qualitatively and quantitatively in comparison with that of a coherent PSK system.

Simon, M. K.↗
NASA NTRS1972

Handbook of operation and maintenance instructions for Model 5208A bit synchronizer unit

Electrical/mechanical characteristics, operation, theory of operation, parts list, and electrical diagrams for the model 5208A bit synchronizer unit are provided. The unit is capable of performing the functions of bit synchronization and signal conditioning on demodulated wave trains containing amplitude, frequency, and phase distortions, as well as additive noise. Operating frequencies in the 1 to 27 MHz bit rate range are accommodated through the use of discrete frequency plug-in subunits. The unit provides 0 and 180 degree clocks and either a single signal hard decision, or a three bit quantized soft decision data output.

Source record↗
NASA NTRS1993

A low cost alternative to high performance PCM bit synchronizers

The Code Converter/Clock Regenerator (CCCR) provides a low-cost alternative to high-performance Pulse Code Modulation (PCM) bit synchronizers in environments with a large Signal-to-Noise Ratio (SNR). In many applications, the CCCR can be used in place of PCM bit synchronizers at about one fifth the cost. The CCCR operates at rates from 10 bps to 2.5 Mbps and performs PCM code conversion and clock regeneration. The CCCR has been integrated into a stand-alone system configurable from one to six channels and has also been designed for use in VMEbus compatible systems.

Deshong, Bruce↗
NASA NTRS1974

Synthesis and evaluation of phase detectors for active bit synchronizers

Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.

Mcbride, A. L.↗
NASA NTRS1974

Carrier tracking, bit synchronization, and coding for S-band communications links

This paper presents the results of a study of the performance of Viterbi-decoded convolutional codes in the presence of nonideal carrier tracking and bit synchronization. A constraint length 7, rate 1/3 convolutional code and parameters suitable for the space shuttle coded communications links are used. Mathematical models are developed and theoretical and simulation results are obtained to determine the tracking and acquisition performance of the system. It is shown that the combined energy-to-noise degradation due to nonideal carrier tracking and bit synchronization over that required for the ideal tracking case can be held to less than 1.5 dB and that combined carrier tracking and bit timing can be acquired in only a few seconds for the parameters and operating ranges of the space shuttle coded communications links.

Odenwalder, J. P.↗
NASA NTRS1976

Comparison of bit synchronization schemes using AM and summed clocks

This paper considers bit synchronization through the use of a separate clock signal which is either amplitude modulated onto or summed with the data signal. For continuous data transmission, such schemes are known to be inferior, in the sense of efficient use of power, to schemes which derive synchronization directly from the data signal. However, these techniques have application in burst systems such as spacecraft command systems, and in systems where receiver simplicity is more important than power conservation. For systems in which the composite data-clock signal subsequently modulates an RF carrier, it is shown that the summed clock signal performs slightly better than the AM clock signal, and that for both signal types, the optimum allocation of power between data and clock is approximately 9:1.

Geist, J. M.↗
NASA NTRS1975

Performance of a finite phase state bit-synchronization loop with and without sequential filters

A discrete phase state bit-synchronization loop is proposed for synchronization and detection of a binary nonreturn-to-zero (NRZ) process. The general loop model is developed for 11 and 17 phase states with optional sequential loop filter. Loop performance is considered in terms of the phase error density function, rms phase error, and mean time to bit slippage. It is shown that satisfactory loop performance can be achieved at -3 dB SNR through use of sequential loop filters.

Ransom, J. J.↗
NASA NTRS1973

An adaptive bit synchronization algorithm under time-varying environment.

This paper presents an adaptive estimation algorithm for bit synchronization, assuming that the parameters of the incoming data process are time-varying. Experiment results have proved that this synchronizer is workable either judged by the amount of data required or the speed of convergence.

Chow, L. R.↗
NASA NTRS1972

An estimation algorithm with learning feature for an adaptive bit synchronizer.

Description of an on-line optimal (in the sense of linear minimum mean square error) sequential bit synchronizer assuming minimal a priori knowledge of the incoming data. The adaptive synchronization algorithms, implemented on a small computer, are capable of accurately estimating pulse transition time, pulse amplitude, and pulse width by invoking the powerful Gauss-Markov theorem. Numerous simulations indicate that the performance of the synchronizer is satisfactory from the point of view of the amount of data required and the speed of convergence.

Chow, L. R.↗
NASA NTRS1976

High rate bit synchronizer

This report documents the analysis and experimental validation of the performance of various aspects of a high rate bit synchronizer.

Lyon, R. F.↗
NASA NTRS2007

Lessons Learned in the Specification, Purchase, Validation and Final Installation Process of a Replacement PCM Bit Synchronizer

This paper intends to describe the lessons learned while specifying validating and installing a bit sync to replace the 30 year old Aydin Model 335a PCM bit sync used in the Space Shuttle Launch Control Center. The engineer had to analyze the original requirements and specifications and then create new requirements documentation that more correctly described our needs. One issue to consider was the removal of unnecessary requirements such as various data formats when only one format is used. The conversion to a system that no longer has an assortment of analog rotary switches required retraining of the operators. Finally, post-procurement corrections for undisclosed user requirements and missed design requirements required close contact with a manufacturer who was willing to accommodate the changes.

Price, Richard N.↗