SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
We describe a software emulator of the MIL-STD-1750A architecture that executes 1750A code at a rate of about 4 MIPS on a Sun 200MHz Ultra2 work-station, and effectively several times faster than that when application-specific optimizations are used.
A design approach for a support system or test station necessary to functionally operate a very high-speed integrated circuit (VHSIC) microprocessor brassboard is presented. Major subsystems which make up the support are the following: (1) power supply unit; (2) temperature controller unit; (3) input/output module; and (4) mechanical test fixture. Theoretical analyses and experimental techniques were utilized to design and implement the power and temperature requirements for the VHSIC processor. A functional description of the input/output module and test fixture is discussed. The support system provides the means to evaluate and functionally test a VHSIC microprocessor.
This paper presents the development of onboard computing improvements for NASA's Multimission Modular Spacecraft. The first MMS spacecraft being enhanced by an additional flight computer is the Explorer Platform. The selection process for both the flight hardware (MIL-STD-1750A Co-Processor) and flight software (Ada high level language) are discussed, followed by the lessons learned during the last three years.
The results of the initial testing of the Generalized Gate Level Logic Simulator (GGLOSS) are discussed. The simulator is a special purpose fault simulator designed to assist in the analysis of the effects of random hardware failures on fault tolerant digital computer systems. The testing of the simulator covers two main areas. First, the simulation results are compared with data obtained by monitoring the behavior of hardware. The circuit used for these comparisons is an incomplete microprocessor design based upon the MIL-STD-1750A Instruction Set Architecture. In the second area of testing, current simulation results are compared with experimental data obtained using precursors of the current tool. In each case, a portion of the earlier experiment is confirmed. The new results are then viewed from a different perspective in order to evaluate the usefulness of this simulation strategy.
This paper describes the attitude determination algorithm for the Explorer Platform satellite. The algorithm, which is baselined on the Landsat code, is a six-element linear quadratic state estimation processor, in the form of a Kalman filter augmented by an adaptive filter process. Improvements to the original Landsat algorithm were required to meet mission pointing requirements. These consisted of a more efficient sensor processing algorithm and the addition of an adaptive filter which acts as a check on the Kalman filter during satellite slew maneuvers. A 1750A processor will be flown on board the satellite for the first time as a coprocessor (COP) in addition to the NASA Standard Spacecraft Computer. The attitude determination algorithm, which will be resident in the COP's memory, will make full use of its improved processing capabilities to meet mission requirements. Additional benefits were gained by writing the attitude determination code in Ada.
The Centaur avionics suite is undergoing a dramatic modernization for the commercial, DoD Atlas and Titan programs. The system has been upgraded to the current state-of-the-art in ring laser gyro inertial sensors and Mil-Std-1750A processor technology. The Cruise Missile avionic system has similarly been evolving for many years. Integration of GPS into both systems has been underway for over five years with a follow-on cruise missile system currently in flight test. Rendezvous and Docking related studies have been conducted for over five years in support of OMV, CTV, and Advanced Upper Stages, as well as several other internal IR&D's. The avionics system and AR&D simulator demonstrated to the SATWG in November 1990 has been upgraded considerably under two IR&D programs in 1991. The Centaur modern avionics system is being flown in block upgrades which started in July of 1990. The Inertial Navigation Unit will fly in November of 1991. The Cruise Missile avionics systems have been fully tested and operationally validated in combat. The integrated AR&D system for space vehicle applications has been under development and testing since 1990. A Joint NASA / GD ARD&L System Test Program is currently being planned to validate several aspects of system performance in three different NASA test facilities in 1992.
The avionics system for the Centaur upper stage is in the process of being modernized with the current state-of-the-art in strapdown inertial guidance equipment. This equipment includes an integrated flight control processor with a ring laser gyro based inertial guidance system. This inertial navigation unit (INU) uses two MIL-STD-1750A processors and communicates over the MIL-STD-1553B data bus. Commands are translated into load activation through a Remote Control Unit (RCU) which incorporates the use of solid state relays. Also, a programmable data acquisition system replaces separate multiplexer and signal conditioning units. This modern avionics suite is currently being enhanced through independent research and development programs to provide autonomous rendezvous and docking capability using advanced cruise missile image processing technology and integrated GPS navigational aids. A system concept was developed to combine these technologies in order to achieve a fully autonomous rendezvous, docking, and autoland capability. The current system architecture and the evolution of this architecture using advanced modular avionics concepts being pursued for the National Launch System are discussed.
A development status evaluation is presented for efforts conducted at NASA-Langley since 1977, toward the characterization of the latent fault in digital fault-tolerant systems. Attention is given to the practical, high speed, generalized gate-level logic system simulator developed, as well as to the validation methodology used for the simulator, on the basis of faultable software and hardware simulations employing a prototype MIL-STD-1750A processor. After validation, latency tests will be performed.