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Study of CMOS strip sensor for future silicon tracker
Monolithic silicon sensors developed with High-Voltage CMOS (HV-CMOS) processes have become highly attractive for charged particle tracking. Compared with the standard CMOS sensors, HV-CMOS sensors can provide larger and deeper depletion regions that lead to larger signals and faster charge collection. They can provide high position resolution, low material budget, high radiation hardness and low cost that are desirable for high performance tracking in harsh collision environment. Various studies have been conducted to explore the technology feasibility for the large-area tracking systems at future collider experiments. CHESS (CMOS HV/HR Evaluation for Strip Sensor) sensor series have been developed as an alternative solution to the conventional silicon micro-strip detectors for the ATLAS inner tracker upgrade. The first prototype (named CHESS1) was to evaluate the diode geometry and the in-pixel analog electronics. Obtained test results were used to optimize the second prototype (named CHESS2). CHESS2 was implemented with a full digital readout architecture and realized as a full reticle sized monolithic sensor. Here, the basic characteristics of the CHESS2 prototype sensors and their performance in response to different input signals are presented.
A Cryogenic readout integrated circuit with analog pile-up and in-Pixel ADC for high frame rate Skipper CCD-in-CMOS Sensors
The Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is designed to enable high frame rate readout of Skipper CCD-in-CMOS image sensors. The SPROCKET2 pixel is fabricated in a 65 nm CMOS process and occupies a 60$\mu$m $\times$ 60$\mu$m footprint. SPROCKET2 is intended to be heterogeneously integrated with a pixelated Skipper CCD-in-CMOS sensor, such that one readout pixel is connected to a multiplexed array of 16 active image sensor pixels, to match their spatial geometry. Our design benefits from the Skipper CCD-in-CMOS sensor's non-destructive readout capability to achieve exceptionally low noise through multi-sampling and averaging while optimizing for total power consumption. The pixel readout utilizes correlated double sampling to minimize 1/f noise and includes "pile-up" of ten successive samples in the analog domain before digitizing at a rate of 66.7 ksps. Measurement results of in-pixel serial SAR ADC show DNL and INL of ~0. 44 LSB and 0.58 LBS respectively. A large area array of 20,000 SPROCKET2 ADC pixels (multiplexed 1:16 to 320,000 sensor pixels) is currently under test. By reading out data over a 10 Gbps optical link, this pixel design enables a frame rate of $\sim$ 4 kfps for large sensing areas with minimal sensing deadtime. In the highest gain mode, the pixelated ADC has an input-referred resolution of 10$\mu$V with a simulated power consumption of 50$\mu$W. The pixel operates with constant current draw to minimize power-rail crosstalk.
A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors
The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.
Overview of CMOS Sensors for Future Tracking Detectors
Depleted Complementary Metal-Oxide-Semiconductor (CMOS) sensors are emerging as one of the main candidate technologies for future tracking detectors in high luminosity colliders. Their capability of integrating the sensing diode into the CMOS wafer hosting the front-end electronics allows for reduced noise and higher signal sensitivity, due to the direct collection of the sensor signal by the readout electronics. They are suitable for high radiation environments due to the possibility of applying high depletion voltage and the availability of relatively high resistivity substrates. The use of a CMOS commercial fabrication process leads to their cost reduction and allows faster construction of large area detectors. In this contribution, a general perspective of the state of the art of CMOS detectors for High Energy Physics experiments is given. The main developments carried out with regard to these devices in the framework of the CERN RD50 collaboration are summarized.
High-Voltage CMOS Active Pixel Sensor
The high-voltage CMOS (HVCMOS) sensors are a novel type of CMOS active pixel sensors for ionizing particles that can be implemented in CMOS processes with deep n-well option. The pixel contains one sensor electrode formed with a deep n-well implanted in a p-type substrate. CMOS pixel electronics, embedded in shallow wells, are placed inside the deep n-well. By biasing the substrate with a high negative voltage and by the use of a lowly doped substrate, a depleted region depth of at least 30 µm can be achieved. The electrons generated by a particle are collected by drift, which induces fast detectable signals. This publication presents a 4.2-cm 2 large HVCMOS pixel sensor implemented in a commercial 180-nm process on a lowly doped substrate and its characterization.
Skipper-in-CMOS: Nondestructive Readout With Subelectron Noise Performance for Pixel Detectors
The Skipper-in-CMOS image sensor integrates the nondestructive readout capability of skipper charge coupled devices (Skipper-CCDs) with the high conversion gain of a pinned photodiode (PPD) in a CMOS imaging process while taking advantage of in-pixel signal processing. This allows both single photon counting as well as high frame rate readout through highly parallel processing. The first results obtained from a ${15} \times {15}~\mu $ m2 pixel cell of a Skipper-in-CMOS sensor fabricated in Tower Semiconductor’s commercial 180-nm CMOS image sensor process are presented. Measurements confirm the expected reduction of the readout noise with the number of samples down to deep subelectron noise of $0.15\text {e}^ - $ , demonstrating the charge transfer operation from the PPD and the single photon counting operation when the sensor is exposed to light. This article also discusses new testing strategies employed for its operation and characterization.
Soft X-ray quantum efficiency of a commercial CMOS imaging sensor
The demonstrated performance and cost-effectiveness of complementary metal-oxide-semiconductor (CMOS) sensors make them a potentially attractive option for low-cost space-based X-ray observatories. We have previously reported on the performance of a commercially available backside-illuminated Sony IMX290LLR-C CMOS sensor and found it to offer X-ray spectral resolutions comparable to the charged coupled devices (CCDs) aboard Suzaku and Chandra and to have a sufficient radiation hardness for use in low Earth orbit. Here, in this work, we report on the quantum efficiency (QE) of this sensor, an essential metric for modeling the sensitivity of an instrument as an X-ray detector. Using the Advanced Photon Source at Argonne National Laboratory, we measure the soft X-ray QE of this CMOS sensor to be 0.28 ± 0.02 at a photon energy of 490.5 eV. This energy was chosen for its proximity to the astrophysically important O VII triplet emission lines (~574 eV) studied by the HaloSat mission. Although not surpassing that of the back-illuminated CCDs aboard Suzaku and Chandra, this QE compares favorably to that of the front-illuminated CCDs aboard the same observatories and is competitive with that of the silicon drift detectors used aboard HaloSat, making it a strong candidate for use on future X-ray small satellite (SmallSat) missions.
Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology
This paper reports the design and process flow for monolithic integration of lateral high voltage (HV) power MOSFET with low voltage (LV) CMOS circuits for SiC Power IC technology. The reported devices and circuits are fabricated on a N-/N+ 4H-SiC substrate at 150mm, production grade- Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose. Here, the static performance characteristics of HV NMOS and LV CMOS are reported. For future high temperature applications, the static performances are fully characterized and are reported up to 200oC. Finally, to validate the fabricated CMOS, a 5-stage ring oscillator is also demonstrated.
Solution-processable integrated CMOS circuits based on colloidal CuInSe2 quantum dots
Abstract The emerging technology of colloidal quantum dot electronics provides an opportunity for combining the advantages of well-understood inorganic semiconductors with the chemical processability of molecular systems. So far, most research on quantum dot electronic devices has focused on materials based on Pb- and Cd chalcogenides. In addition to environmental concerns associated with the presence of toxic metals, these quantum dots are not well suited for applications in CMOS circuits due to difficulties in integrating complementary n - and p -channel transistors in a common quantum dot active layer. Here, we demonstrate that by using heavy-metal-free CuInSe 2 quantum dots, we can address the problem of toxicity and simultaneously achieve straightforward integration of complimentary devices to prepare functional CMOS circuits. Specifically, utilizing the same spin-coated layer of CuInSe 2 quantum dots, we realize both p - and n -channel transistors and demonstrate well-behaved integrated logic circuits with low switching voltages compatible with standard CMOS electronics.
Design of microwave broadband CMOS transmitter and receiver circuits for MIR and ECEI plasma diagnostics
To efficiently determine the plasma electron density fluctuations using the MIR diagnostic technique, a 55–75 GHz 65 nm-CMOS transmitter has been developed where four separate intermediate frequency (IF) signals are up-converted, amplified, and then combined to generate an 8-tone RF output; a broadband 90 nm-CMOS receiver has also been constructed, which consists of an RF-low noise amplifier (LNA), mixer, and IF amplifier. The circuits and their corresponding modules will soon be deployed on the DIII-D and NSTX-U fusion devices. A 110–140 GHz 65 nm-CMOS receiver has also been designed, which is suitable for measuring the deep-core temperature fluctuations in the DIII-D tokamak using the electron cyclotron emission imaging diagnostic system. In addition to the RF-LNA/balun, mixer, and IF amplifier, an LO balun/tripler and driving amplifier are now included in this highly integrated circuit chip. By adopting the microwave and millimeterwave system-on-chip concept in the front-end system design, this paper demonstrates that compact transmitter and receiver modules can be easily built, which, in turn, facilitates array implementation and maintenance.
CMOS-Based Single-Cycle in-Memory XOR/XNOR
Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a massive amount of securely backed-up data is required for training binary convolutional neural networks for image classification. XOR and XNOR operations are essential for large-scale data copy verification, encryption, and classification algorithms. The disproportionate speed of existing compute and memory units makes the von Neumann architecture inefficient to perform these Boolean operations. Compute-in-memory (CiM) has proved to be an optimum approach for such bulk computations. The existing CiM-based XOR/XNOR techniques either require multiple cycles for computing or add to the complexity of the fabrication process. Here, we propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations. Our design provides at least 2× improvement in the latency compared with other existing CMOS-compatible solutions. We verify the proposed system through circuit/system-level simulations and evaluate its robustness using a 5000-point Monte Carlo variation analysis. This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.
CMS HGCAL ECON-D ASIC : Impact of CMOS fabrication process tuning on performance and radiation tolerance
The CMS experiment’s High Granularity Calorimeter (HGCAL) upgrade will replace CMS’s existing endcap calorimeters in preparation for the High Luminosity LHC. To effectively use over 6 million channels of this “imaging”calorimeter, CMS has developed two novel Endcap Concentrator (ECON) ASICs to perform data compression/selection on detector. The ECON-D ASIC operates on the 750kHz data path, and the ECON-T ASIC on the 40MHz trigger path. These 65 nm CMOS ASICs are radiation tolerant to 200 Mrad and low power, operating at less than 2.5 mW/channel. The first full-functionality prototype ECONs were produced and characterized in 2021-23, and an initial engineering run was performed in 2024. ECON-D radiation testing for the engineering run revealed that the chip’s internal SRAMs produce intermittent read errors for a non-negligible fraction of chips. Further investigation indicated that the SRAM performance is highly sensitive to the exact parameters of the CMOS fabrication process. To both study this process sensitivity and mitigate SRAM performance issues, twenty ECON wafers were produced in 2025 with a range of doping concentrations designed to tune the underlying transistor threshold voltage by 0%, 5%, 10%, and 15% from nominal. This talk will present first measurements of ECON-D performance, power consumption, and radiation tolerance for these four variations of CMOS process.
Ultrafast CMOS image sensors and data-enabled super-resolution for multimodal radiographic imaging and tomography
We summarize recent progress in ultrafast Complementary Metal Oxide Semiconductor (CMOS) image sensor development and the application of neural networks for post-processing of CMOS and charge-coupled device (CCD) image data to achieve sub-pixel resolution (thus ‘super-resolution’). The combination of novel CMOS pixel designs and data-enabled image post-processing provides a promising path towards ultrafast high-resolution multi-modal radiographic imaging and tomography applications.
Ultrafast CMOS image sensors and data-enabled super-resolution for multimodal radiographic imaging and tomography
We summarize recent progress in ultrafast Complementary Metal Oxide Semiconductor (CMOS) image sensor development and the application of neural networks for post-processing of CMOS and charge-coupled device (CCD) image data to achieve sub-pixel resolution (thus $super$-$resolution$). The combination of novel CMOS pixel designs and data-enabled image post-processing provides a promising path towards ultrafast high-resolution multi-modal radiographic imaging and tomography applications.
Soft x-ray detection for small satellites with a commercial CMOS sensor at room temperature
Recently CMOS (complementary metal-oxide-semiconductor) sensors have progressed to a point where they may offer improved performance in imaging x-ray detection compared to the CCDs often used in x-ray satellites. We demonstrate x-ray detection in the soft x-ray band (250-1700 eV) by a commercially available back-illuminated Sony IMX290LLR CMOS sensor using the Advanced Photon Source at the Argonne National Laboratory. Additionally, while operating the device at room temperature, we measure energy resolutions (FWHM) of 47 eV at 250 eV and and 77 eV 1700 eV which are comparable to the performance of the Chandra ACIS and the Suzaku XIS. Furthermore, we demonstrate that the IMX290LLR can withstand radiation up to 17.1 krad, making it suitable for use on spacecraft in low earth orbit.
A 30‐GHz low‐power CMOS LNA for 5G communication systems
Abstract This paper presents theoretical analysis and design procedures for low noise amplifiers (LNAs) in advanced CMOS technologies. For demonstration, a 30‐GHz LNA designed for 5G millimeter‐wave communication systems was fabricated in a 65‐nm CMOS process. It provides a power gain of 22.6 dB with a noise figure of 3.2 dB while drawing 7.3 mW from a 1.2 V supply.
AstroPix4 — a novel HV-CMOS sensor developed for space based experiments
For the proposed space based gamma-ray observatory All-sky Medium-Energy Gamma-ray Observatory eXplorer (AMEGO-X), a silicon tracker based on a novel High Voltage-CMOS (HV-CMOS) sensor called AstroPix, is currently being developed. Preliminary measurements with the first full reticle prototype AstroPix3 show that the power target of 1.5 mW/cm 2 can currently not be reached due to the digital consumption of 3.08 mW/cm 2 , while the analog power consumption of 1.04 mW/cm 2 and a break down voltage of over 350 V look promising. Based on these results, the design changes in AstroPix4, submitted in May 2023, are presented, containing changes to the time stamp generation and readout architecture. A digital power consumption below 0.25 mW/cm 2 is expected by removing the fast 200 MHz clock used to measure the time-over-threshold (ToT) and an LVDS receiver. A maximum resolution of 3.125 ns for time-of-arrival (ToA) and ToT is reached by adding per-pixel Flash-Time-to-Digital Converter (TDCs) controlled by a global delay-locked loop (DLL).