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The 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Clock generators, waveform generation, signal shaping and conditioning, digital to analog conversion, and analog to digital conversion are discussed.
PCIO card in input/output interface-circuit card enabling computer based on ISA bus to transmit and receive high-speed, synchronous serial data and clock signals. Designed specifically to plug into IBM PC-AT or compatible computer and to handle input and output of data in packet formats like those of telemetric data streams used throughout NASA and aerospace industry. Reduces amount of auxiliary equipment needed.
System measures timing errors between signals produced by three asynchronous time-code generators. Errors between 1-second clock pulses resolved to 2 microseconds. Basic principle of computation of timing errors as follows: central processing unit in microcontroller constantly monitors time data received from time-code generators for changes in 1-second time-code intervals. In response to any such change, microprocessor buffers count of 16-bit internal timer.
The symposium presented issues involved in the development of scheduling systems that can deal with resource and time limitations. To qualify, a system must be implemented and tested to some degree on non-trivial problems (ideally, on real-world problems). However, a system need not be fully deployed to qualify. Systems that schedule actions in terms of metric time constraints typically represent and reason about an external numeric clock or calendar and can be contrasted with those systems that represent time purely symbolically. The following topics are discussed: integrating planning and scheduling; integrating symbolic goals and numerical utilities; managing uncertainty; incremental rescheduling; managing limited computation time; anytime scheduling and planning algorithms, systems; dependency analysis and schedule reuse; management of schedule and plan execution; and incorporation of discrete event techniques.
In a time-dependent three dimensional MHD simulation for cometary plasmas, Schmidt-Voigt (1989) could observe the formation of condensations in the plasma tail after a 90 degree change in the interplanetary magnetic field (IMF) sweeping over the comet. We investigated the IMF measurements of the Vega SC in the vicinity of the comet Halley for 90 degree changes in the clock angle and studied the relation between them and optical observations of condensations in the plasma tail. For the time interval 24 Feb. 86 to 14 Mar. 86, we could not find a correlation between such changes and the release of condensations from the cometary head.
For space operations from the Space Station Freedom the real time range imager will be very valuable in terms of refuelling, docking as well as space exploration operations. For these applications as well as many other robotics and remote ranging applications, a small potable, power efficient, robust range imager capable of a few tens of km ranging with 10 cm accuracy is needed. The system developed is based on a well known pseudo-random modulation technique applied to a laser transmitter combined with a novel range resolution enhancement technique. In this technique, the transmitter is modulated by a relatively low frequency of an order of a few MHz to enhance the signal to noise ratio and to ease the stringent systems engineering requirements while accomplishing a very high resolution. The desired resolution cannot easily be attained by other conventional approaches. The engineering model of the system is being designed to obtain better than 10 cm range accuracy simply by implementing a high precision clock circuit. In this paper we present the principle of the pseudo-random noise (PN) lidar system and the results of the proof of experiment.
In this paper, an analysis and hardware emulation of the tracking loops for a very flexible programmable digital modem (PDM) will be presented. The modem is capable of being programmed for 2, 4, 8, 16-PSK, 16-QAM, MSK, and Offset-QPSK modulation schemes over a range of data rates from 2.34 to 300 Mbps with programmable spectral occupancy from 1.2 to 1.8 times the symbol rate; these operational parameters are executable in burst or continuous mode. All of the critical processing in both the modulator and demodulator is done at baseband with very high-speed digital hardware and memory. Quadrature analog front-ends are used for translation between baseband and the IF center frequency. The modulator is based on a table lookup approach, where precomputed samples are stored in memory and clocked out according to the incoming data pattern. The sample values are predistorted to counteract the effects of the other filtering functions in the link as well as any transmission impairments. The demodulator architecture was adapted from a joint estimator-detector (JED) mathematical analysis. Its structure is applicable to most signalling formats that can be represented in a two-dimensional space. The JED realization uses interdependent, mutually aiding tracking loops with post-detection data feedback. To expedite and provide for more reliable synchronization, initial estimates for these loops are computed in a parallel acquisition processor. The cornerstone of the demodulator realization is the pre-averager received data filter which allows operation over a broad range of data rates without any hardware changes and greatly simplifies the implementation complexity. The emulation results confirmed tracking loop operation over the entire range of operational parameters listed above, as well as the capability of achieving and maintaining synchronization at BER's in excess of 10(exp -1). The emulation results also showed very close agreement with the tracking loop analysis, and validated the resolution apportionment of the various hardware elements in the tracking loops.
This report documents construction and testing of the Interferometric Tracking System project developed under the NASA SBIR contract NAS5-30313. Manuals describing the software and hardware, respectively entitled: 'Field Station Guide to Operations' and 'Field Station Hardware Manual' are included as part of this final report. The objective of this contract was to design, build, and operate a system of three ground stations using Very Long Baseline Interferometry techniques to measure the TDRS orbit. The ground stations receive signals from normal satellite traffic, store these signals in co-located computers, and transmit the information via phone lines to a central processing site which correlates the signals to determine relative time delays. Measurements from another satellite besides TDRS are used to determine clock offsets. A series of such measurements will ultimately be employed to derive the orbital parameters, yielding positions accurate to within 50 meters or possibly better.
Most of the known linguistic models are essentially static, that is, time is not a parameter in describing the behavior of the object's model. In this paper we show a model for synchronous finite state machines based on fuzzy logic. Such finite state machines can be used to build both event-driven, time-varying, rule-based systems and the control unit section of a fuzzy logic computer. The architecture of a pipelined intelligent fuzzy controller is presented, and the linguistic model is represented by an overall fuzzy relation stored in a single rule memory. A VLSI integrated circuit implementation of the fuzzy controller is suggested. At a clock rate of 30 MHz, the controller can perform 3 MFLIPS on multi-dimensional fuzzy data.
As processor performance gains continue to outstrip Input/Output gains, I/O performance is becoming critical to overall system performance. File read latency is the most significant bottleneck for high performance I/O. Other aspects of I/O performance benefit from recent advances in disk bandwidth and throughput resulting from disk arrays, and in write performance derived from buffered write behind and the Log-structured File System. The access gap problem limiting improvements in read latency is exacerbated by distributed file systems operating over networks with diverse bandwidth. Focus is on extending the power of caching and prefetching to reduce file read latencies by exploiting hints from high-levels of a system. Such Transparent Informed Prefetching, TIP, and its benefits are described. It is argued that hints that disclose high level knowledge are a means for transferring optimization information across, without violating, module boundaries. How TIP can be used to convert the high throughput of new technologies such as disk arrays and log-structured file systems into low latency for applications is discussed. Our preliminary experiments show reductions in wall - clock execution time of 13 percent and 20 percent for a multiple module compilation tool (make) accessing data on a local disk and remote Coda file server, respectively, and a reduction of 30 percent for a text search (grep) remotely accessing many small files.
A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.
In a distributed memory multicomputer that has no global clock, global processor synchronization can only be achieved through software. Global synchronization algorithms are used in tridiagonal systems solvers, CFD codes, sequence comparison algorithms, and sorting algorithms. They are also useful for event simulation, debugging, and for solving mutual exclusion problems. For the Intel iPSC/860 in particular, global synchronization can be used to ensure the most effective use of the communication network for operations such as the shift, where each processor in a one-dimensional array or ring concurrently sends a message to its right (or left) neighbor. Three global synchronization algorithms are considered for the iPSC/860: the gysnc() primitive provided by Intel, the PICL primitive sync0(), and a new recursive doubling synchronization (RDS) algorithm. The performance of these algorithms is compared to the performance predicted by communication models of both the long and forced message protocols. Measurements of the cost of shift operations preceded by global synchronization show that the RDS algorithm always synchronizes the nodes more precisely and costs only slightly more than the other two algorithms.
High temperature superconductor (HISC) materials and devices can provide immediate applications for many space missions. The in-space thermal environment provides an opportunity to develop, test, and apply this technology to enhance performance and reliability for many applications of crucial importance to NASA. Specifically, the technology development areas include: (1) high current power transmission, (2) microwave components, devices, and antennas, (3) microwave, optical, and infrared sensors, (4) signal processors, (5) submillimeter wave components and systems, (6) ultra stable space clocks, (7) electromagnetic launch systems, and (8) accelerometers and position sensors for flight operations. HTSC is expected to impact NASA's Lunar Bases, Mars exploration, Mission to Earth, and Planetary exploration programs providing enabling and cost-effect technology. A review of the space applications of the HTSC technology is presented. Problem areas in technology development needing special attention are identified.
The Allan variance for an averaging time tau can be estimated either from all available phase samples or from a subgrid of samples with spacing tau. This paper gives a set of computational recipes that yield the variance of both estimators, with less than 2 percent error, for the five power-law components of the classical continuous-time clock noise model.
Observations of PSR 0531+21 with the High Speed Photometer on the HST in the visible in October 1991 and in the UV in January 1992 are presented. The time resolution of the instrument was 10.74 microsec; the effective time resolution of the light curves folded modulo the pulsar period was 21.5 microsec. The main pulse arrival time is the same in the UV as in the visible and radio to within the accuracy of the establishment of the spacecraft clock, +/- 1.05 ms. The peak of the main pulse is resolved in time. Corrected for reddening, the intensity spectral index of the Crab pulsar from 1680 to 7400 A is 0.11 +/- 0.13. The pulsed flux has an intensity less than 0.9 percent of the peak flux just before the onset of the main pulse. The variations in intensity of individual main and secondary pulses are uncorrelated, even within the same rotational period.
The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.
From the October 1989 launch to the first December 1990 earth gravity assist, we regularly obtained frequency measurements of the spacecraft clock - an ultrastable crystal oscillator (USO) supplied by Frequency Electronics, Inc. The solar gravitational redshift in frequency was readily detectable, and because of the unique variations in heliocentric distance we could separate the general relativistic effects from the USO's intrinsic frequency variations. We have verified the total frequency shift predicted by general relativity to 0.5 percent accuracy, and the solar gravitational redshift to 1 percent accuracy.
We have analyzed the longitude distributions of major flares observed in the 1955-1991 interval, referring them to coordinate systems rotating about axes tilted with respect to the rotation axis of the solar envelope. We find that the longitude distribution exhibits the largest modulation in the coordinate system with the following parameters: rotation period, 25.50 days; tilt angle of the rotation axis, 40 deg; tilt direction, toward the position of the earth on December 4 in its orbit around the sun. We interpret this as being due to an obliquely rotating structure (or a wave pattern rotating about an oblique axis) which has two exciters. We identify the period of 25.50 days as the fundamental period of the hypothetical 'clock' proposed by Bai and Sturrock (1991). The periods of the subharmonics are 51.0, 76.5, 102.0, 127.5, and 153.0 days, in agreement with periodicities found from analysis of flare occurrence times.