Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Transistors”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 1,765 records · Page 98
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

High Power SiGe X-Band (8-10 GHz) Heterojunction Bipolar Transistors and Amplifiers

Limited by increased parasitics and thermal effects as the device size becomes large, current commercial SiGe power HBTs are difficult to operate at X-band (8-12 GHz) with adequate power added efficiencies at high power levels. We found that, by changing the heterostructure and doping profile of SiGe HBTs, their power gain can be significantly improved without resorting to substantial lateral scaling. Furthermore, employing a common-base configuration with proper doping profile instead of a common-emitter configuration improves the power gain characteristics of SiGe HBTs, which thus permits these devices to be efficiently operated at X-band. In this paper, we report the results of SiGe power HBTs and MMIC power amplifiers operating at 8-10 GHz. At 10 GHz, 22.5 dBm (178 mW) RF output power with concurrent gain of 7.32 dB is measured at the peak power-added efficiency of 20.0% and the maximum RF output power of 24.0 dBm (250 mW) is achieved from a 20 emitter finger SiGe power HBT. Demonstration of single-stage X-band medium-power linear MMIC power amplifier is also realized at 8 GHz. Employing a 10-emitter finger SiGe HBT and on-chip input and output matching passive components, a linear gain of 9.7 dB, a maximum output power of 23.4 dBm and peak power added efficiency of 16% is achieved from the power amplifier. The MMIC exhibits very low distortion with third order intermodulation (IM) suppression C/I of -13 dBc at output power of 21.2 dBm and over 20dBm third order output intercept point (OIP3).

Ma, Zhenqiang↗
NASA NTRS1991

Passively forced current sharing among transistors

This application concerns a simple passive circuit that improves current balance in paralleled power MOSFETs that are not precisely matched and that are operated in their active region from a common gate drive. A nonlinear circuit consisting of diodes and resistors generates a differential gate potential required to correct for unbalance while maintaining low losses over a range of current.

Niedra, Janis M.↗
NASA NTRS2005

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Fossum, Eric R.↗
NASA NTRS1989

Monolithic transistor gate energy recovery system

Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period .DELTA.T given by ##EQU1## L.sub.s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C.sub.in is the capacitance of that switch between its gate and source electrodes. The interval .DELTA.T may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v.sub.g and comparing it with fixed progressively higher voltages v.sub.1, v.sub.2 and v.sub.3, where v.sub.2 is intermediate v.sub.1 and v.sub.3 which correspond to the lower and upper levels of v.sub.g as the switch is turned off and on.

Rippel, Wally E.↗
NASA NTRS2005

Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

CMOS integrated circuits↗
NASA NTRS2009

A Mathematical Model of a Simple Amplifier Using a Ferroelectric Transistor

This paper presents a mathematical model characterizing the behavior of a simple amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the amplifier is the basis of many circuit configurations, a mathematical model that describes the behavior of a FeFET-based amplifier will help in the integration of FeFETs into many other circuits.

Sayyah, Rana↗
NASA NTRS2010

Modeling a Common-Source Amplifier Using a Ferroelectric Transistor

This paper presents a mathematical model characterizing the behavior of a common-source amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the common-source amplifier is the most widely used amplifier in MOS technology, understanding and modeling the behavior of the FeFET-based common-source amplifier will help in the integration of FeFETs into many circuits.

Sayyah, Rana↗
NASA NTRS2004

Self-Recovery Experiments in Extreme Environments Using a Field Programmable Transistor Array

Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. However, current technology can only ensure very limited lifetime in extreme environments. This paper describes novel experiments that allow adaptive in-situ circuit redesign/reconfiguration during operation in extreme temperature and radiation environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip (FPTA-2), which recovers functionality for temperatures until 28 C and with total radiation dose up to 250kRad.

space vehicle electronics↗
NASA NTRS2011

Four-gate transistor analog multiplier circuit

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Mojarradi, Mohammad M.↗
NASA NTRS2004

High temperature experiments using programmable transistor array

Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques such as bias cancellation circuitry have also been employed. However, current technology can only ensure very limited lifetime in extreme environments. This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in-situ circuit redesign/reconfiguration during operation in extreme environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip, which recovers functionality until 280oC. We show in this paper the functionality recovery at high temperatures for a variety of circuits, including rectifiers, amplifiers and filters.

Duong, Vu↗