Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs
This report introduces signal-flow graphs for linear time-periodic systems to streamline and visually describe the frequency-domain modeling of complex phase-locked loop (PLL) systems used in grid-connected converters. Small-signal modeling using the proposed graphs is demonstrated for two commonly used single-phase PLL structures: SOGI-PLL and Park-PLL. Loop-gain models are developed for these PLLs to evaluate how an orthogonal signal generator (OSG), which is required in single-phase PLLs using the synchronous reference frame (SRF) architecture, modifies the PLL loop-gain compared to that of a three-phase SRF-PLL, which does not require an OSG. It is shown that the OSG in the SOGI-PLL and Park-PLL introduces significant phase-lag in the PLL loop-gain, limiting the maximum bandwidth for which either PLL can be designed. Slow frequency adaptation (SFA) of OSG is proposed as a solution to mitigate the influence of the OSG dynamics on the PLL loop-gain. Experimental results are presented to validate the developed loop-gain models and show that the proposed SFA-SOGI-PLL and SFA-Park-PLL have improved transient performance, they do not suffer from the bandwidth limit, and they also preserve the steady-state performance of the standard SOGI-PLL and Park-PLL.