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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,711 records · Page 95
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

MST radar transmitter control and monitor system

A generalized transmitter control and monitor card was developed using the Intel 8031 (8051 family) microprocessor. The design was generalized so that this card can be utilized for virtually any control application with only firmware changes. The block diagram appears in Figure 2. The card provides for local control using a 16 key keypad (up to 64 keys are supported). The local display is four digits of 7 segment LEDs. The display can indicate the status of all major system parameters and provide voltage readout for the analog signal inputs. The card can be populated with only the chips required for a given application. Fully populated, the card has two RS-232 serial ports for computer communications. It has a total of 48 TTL parallel lines that can define as either inputs or outputs in groups of four. A total of 32 analog inputs with a 0-5 volt range are supported. In addition, a real-time clock/calendar is available if required. A total of 16 k bytes of ROM and 16 k bytes of RAM is available for programming. This card can be the basis of virtually any monitor or control system with appropriate software.

Brosnahan, J. W.↗
NASA NTRS1984

The VAX/VMS device driver and user operation program for the Midwestern Astronomical Data Reduction and Analysis Facility PDS microdensitometer

The Midwestern astronomical data reduction and analysis facility (MADRAF) PDS microdensitometer which was the first astronomical PDS which was provided with a Motorola 6800 microprocessor control/interface and will be interfaced to a 32-bit instruction computer operating in a multiuser environment is outlined. Command and response handshaking are handled on an RS 232 serial line while data transfer occurs on a dedicated Direct Memory Access line. This set of conditions necessitated the creation of a specialized device for the system. The general outline of this software is discussed. The availability of an extraordinarily powerful computer opened the possibility of a user operating program of great versatility with diverse data destinations and formats, automatic documentation, and an extensive set of utilities which facilitate operations.

Anderson, C. M.↗
NASA NTRS1984

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗
NASA NTRS1984

Research in the design of high-performance reconfigurable systems

An initial design for the Bit Processor (BP) referred to in prior reports as the Processing Element or PE has been completed. Eight BP's, together with their supporting random-access memory, a 64 k x 9 ROM to perform addition, routing logic, and some additional logic, constitute the components of a single stage. An initial stage design is given. Stages may be combined to perform high-speed fixed or floating point arithmetic. Stages can be configured into a range of arithmetic modules that includes bit-serial one or two-dimensional arrays; one or two dimensional arrays fixed or floating point processors; and specialized uniprocessors, such as long-word arithmetic units. One to eight BP's represent a likely initial chip level. The Stage would then correspond to a first-level pluggable module. As both this project and VLSI CAD/CAM progress, however, it is expected that the chip level would migrate upward to the stage and, perhaps, ultimately the box level. The BP RAM, consisting of two banks, holds only operands and indices. Programs are at the box (high-level function) and system level. At the system level initial effort has been concentrated on specifying the tools needed to evaluate design alternatives.

Slotnick, D. L.↗
NASA NTRS1983

A versatile ground data display system for Spacelab experiments

A microprocessor-based data capture and display system suited to the needs of many Spacelab experimenters is described. Although developed specifically for the needs of the FAUST UV astronomy telescope, several features of the system may make it attractive to other groups who need to interact with their Spacelab data in real or near-real time. The display system captures data from the serial data stream originating in the Spacelab experiment computer input/output (ECIO) data channel, and can reformat and display several hundred variables per second in real time. The system offers a combination of CRT display and analog paper strip-chart output. A facility is also provided for simultaneously creating floppy-disk records of short segments of data according to prearranged criteria, to allow detailed examination of critical events in the operation of the experiment. The simplicity, economy, reliability, and flexibility of the display system suggest its use for monitoring a variety of low- and medium-data-rate Spacelab experiments.

Werthimer, D.↗
NASA NTRS1982

Baseband processor development for the Advanced Communications Satellite Program

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Moat, D.↗
NASA NTRS1983

Photoelectric photometry of selected SAO stars. III

Photometric observations of 131 SAO stars for use in calibrating data obtained from the Near Infrared Photographic Sky Survey (NIPSS) are reported. The serial numbers of the primary NIPSS program fields in which the photometry was done are shown along with the approximate position of each field and the number of stars observed in each field. The observations are listed, showing the SAO numbers of the program stars, their 1950 equatorial coordinates, the V magnitudes, and the (V-R) and (V-I) color indices. The mean errors in magnitudes and color indices obtained by averaging deviations from the mean for each star are on the order of 0.02 mag.

Scharlach, W. W. G.↗
NASA NTRS1985

Dynamic-RAM Data Storage Unit

Dynamic random-access-memory (RAM) data delay and storage unit developed to insure data received from satellite is stored and not lost when satellite is not within range of ground station. Stores 256K of serial data, with independent read and write capability.

Sturman, J. C.↗
NASA NTRS1986

Conductive Container for Semiconductor Devices

Container for semiconductor components not only protects them against mechanical damage but ensures they are not harmed by electrostatic discharges. Container holds components in fixed positions so they can be serialized and identified from their locations. Suitable for holding components during both storing and shipping. Originally developed for microwave diodes, container concept readily adaptable to transistors and integrated circuits.

Rice, J. T.↗
NASA NTRS1986

Single-Chip VLSI Reed-Solomon Encoder

Reed-Solomon (RS) encoder based on Berlekamp bit-serial multiplier algorithm. RS code standard, based on code words of 255 8-bit symbols, of which 223 symbols convey information and remaining 32 are check symbols. This code enables correction of up to 16 erroneous information symbols per word. Berlekamp algorithm based on code-generating polynomial with 32 roots that occur in reciprocal pairs. Choice of algorithm permits compact design.

Truong, T. K.↗
NASA NTRS1984

Software used with the flux mapper at the solar parabolic dish test site

Software for data archiving and data display was developed for use on a Digital Equipment Corporation (DEC) PDP-11/34A minicomputer for use with the JPL-designed flux mapper. The flux mapper is a two-dimensional, high radiant energy scanning device designed to measure radiant flux energies expected at the focal point of solar parabolic dish concentrators. Interfacing to the DEC equipment was accomplished by standard RS-232C serial lines. The design of the software was dicated by design constraints of the flux-mapper controller. Early attemps at data acquisition from the flux-mapper controller were not without difficulty. Time and personnel limitations result in an alternative method of data recording at the test site with subsequent analysis accomplished at a data evaluation location at some later time. Software for plotting was also written to better visualize the flux patterns. Recommendations for future alternative development are discussed. A listing of the programs used in the anaysis is included in an appendix.

Miyazono, C.↗
NASA NTRS1984

Fitts' Law? a Test of the Relationship Between Information Load and Movement Precision

The independence of information load (Hick's Law) and movement precision (Fitts' Law) was tested using additive factors methodology. Subjects were required to classify stimuli according to a decision rule with a variable entropy. The stimuli were presented in the center of the CRT screen. In response, subjects had to move a cursor from a starting point near the stimulus to the appropriate target. The precision of the response movement was varied by manipulating the ratio of the radius of the annulus to the width of the target area. The dependent measure was elapsed time between onset of the stimulus and completion of the response movement. Independence of the Hick's Law and Fitts' Law components of the reaction time was tested with an analysis of variance. Presence of an interaction would suggest that a decision stage and a response stage are dependent, and cannot be considered discrete steps in a serial process.

Zalaski, M.↗
NASA NTRS1984

Slow opening valve

A valve control is described having a valve body with an actuator stem and a rotating handle connected to the actuator stem by a differential drive mechanism which, during uniform movement of the handle in one direction, initially opens the valve at a relatively slow rate and, thereafter, complete the valve movement at a substantially faster rate. A series of stop rings are received about the body in frictional abutting relationship and serially rotated by the handle to uniformly resist handle movement independently of the extent of handle movement.

Drapeau, D. F.↗
NASA NTRS1984

Periodic binary sequence generators: VLSI circuits considerations

Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

Perlman, M.↗
NASA NTRS1985

Reactanceless synthesized impedance bandpass amplifier

An active R bandpass filter network is formed by four operational amplifier stages interconnected by discrete resistances. One pair of stages synthesize an equivalent input impedance of an inductance (L sub eq) in parallel with a discrete resistance (R sub o) while the second pair of stages synthesizes an equivalent input impedance of a capacitance (C sub eq) serially coupled to another discrete resistance (R sub i) coupled in parallel with the first two stages. The equivalent input impedances aggregately define a tuned resonant bandpass filter in the roll-off regions of the operational amplifiers.

Kleinberg, L. L.↗
NASA NTRS1985

Graphic displays of vector magnetograph data

Graphic displays that have proved useful in dealing with vector magnetograph data are summarized in three settings: real-time control, analysis, and final presentation. Among the topics discussed are: flexible, implicit data-scaling; geometrical transformations; methods of comparing fields (e.g., transverse vs. longitudinal; observed vs. computed; one time vs. another); displaying the magnitude and direction of the transverse field; minimizing the display time of serial graphics devices; graphic file structure; and graphic interaction with operators and observers.

Rabin, D. M.↗
NASA NTRS1984

Experience with 800 x 800 virtual phase and 500 x 500 three-phase CCD imagers

A description of the Galileo/Institute for Astronomy charge-coupled device (CCD) imaging system and its initial operation has been presented previously. Originally designed to operate a 500 x 500 backside illuminated three-phase CCD, the system has been modified to allow use of either the 500 x 500 sensor or the TI 800 x 800 virtual phase CCD. The modifications for the operation of the virtual phase CCD and current system performance with each type of sensor are discussed. A description is given of the implementation of various techniques discovered at the Jet Propulsion Laboratory that improve imager performance. These techniques include tri-level clocking of the virtual phase CCD to eliminate spurious charge generation in the serial register, the use of ultraviolet light flood with the backside thinned 500 x 500 three-phase device to dramatically improve the quantum efficiency in the blue, and the practical elimination of deferred charge in the three-phase device. Results of astronomical observations with each sensor are presented.

Hlivak, R. J.↗
NASA NTRS1985

Parallel solution of closely coupled systems

An odd-even permutation and a nested dissection technique were used to circumvent the strong seriality of a system of closely coupled equations. The effect of transforming the n x n Hermitian definite positive matrix coefficient on the topology of Cholesky factors is discussed. A series of directed graphs is constructed in order to show the computational steps required for the odd-even permutation. Numerical expressions for the speed-up and efficiency of parallel N-processing techniques and sequential processing by a single computer are derived. Similar expressions are derived for the case of insufficient processing capacity. The application of the odd-even permutation to the ensemble class of computer architectures is demonstrated.

Utku, S.↗