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At least 1,693 records · Page 94

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NASA NTRS1992

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

Cunningham, Thomas J.↗

NASA NTRS1992

Cryogenic measurements of aerojet GaAs n-JFETs

The spectral noise characteristics of Aerojet GaAs n-JFETs have been investigated down to liquid helium temperatures. Voltage noise characterization was performed with the FET in 1) the floating gate mode, 2) the grounded gate mode to determine the lowest noise readings possible and 3) with an extrinsic silicon photodetector at various detector bias voltages, to determine optimum operating conditions. Current noise characterization was measured at the drain in the temperature range 300 to 77 K. Device design and MBE processing are described. Static I-V characterization is done at 300, 77 and 6 K. The measurements indicate that the Aerojet GaAs n-JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered as a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to that of Si MOSFETs operating at liquid helium temperatures, and is equal to the best Si n-JFETs operating at 300 K.

Goebel, John H.↗

NASA NTRS1992

Evaluation of GaAs FETs for cryogenic readout

Low-frequency, low-noise, low-power cryogenic electronics to read out photodetectors is being investigated for the star-tracking telescope of the Gravity Probe B spacecraft. We report our initial findings from evaluating more than 20 types of GaAs FETs, both commercial and non-commercial, for this application. Most exhibit useable dc characteristics at cryogenic temperatures, although gate leakage and hysteretic effects (presumably due to charge trapping) could be troublesome. Low-frequency noise (based primarily on grounded-gate measurements) at 4 K is '1/f-like' and for the quietest GaAs FETs appears to be at least as low as the lowest noise values reported for Si MOSFETs at 4 K. Further investigation is needed in several areas.

Kirschman, Randall K.↗

NASA NTRS1990

Automating analog design: Taming the shrew

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

Barlow, A.↗

NASA NTRS1990

Vertical bloch line memory

Vertical Bloch Line (VBL) memory is a recently conceived, integrated, solid-state, block-access, VLSI memory which offers the potential of 1Gbit/sq cm real storage density, gigabit per second data rates, and sub-millisecond average access times simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBL's are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of VBL pairs are used to store binary information. At present, efforts are being directed at developing a single-chip memory using 25Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. This paper describes the current design architecture, functional elements, and supercomputer simulation results which are used to assist the design process. The current design architecture uses three metal layers, two ion implantation steps for modulating the thickness of the magnetic layer, one ion implantation step for assisting propagation in the major line track, one NiFe soft magnetic layer, one CoPt hard magnetic layer, and one reflective Cr layer for facilitating magneto-optic observation of magnetic structure. Data are stored in a series of elongated magnetic domains, called stripes, which serve as storage sites for arrays of VBL pairs. The ends of these stripes are placed near conductors which serve as VBL read/write gates. A major line track is present to provide a source and propagation path for magnetic bubbles. Writing and reading, respectively, are achieved by converting magnetic bubbles to VBL's and vice versa. The output function is effected by stretching a magnetic bubble and detecting it magnetoresistively. Experimental results from the past design cycle created four design goals for the current design cycle. First, the bias field ranges for the stripes and the major line needed to be matched. Second, the magnetic field barrier between the stripe and the read/write gates needed to be reduced. Third, current conductor routing needed to be improved to reduce occurrences of open-circuiting, short-circuiting, and eddy-current shielding. Fourth, a modified Co-alloy was needed with an increased coercivity and controlled magnetization to allow VBL stabilization to occur without affecting stripe stability.

Katti, R.↗

NASA NTRS1993

Design for testability and diagnosis at the system-level

The growing complexity of full-scale systems has surpassed the capabilities of most simulation software to provide detailed models or gate-level failure analyses. The process of system-level diagnosis approaches the fault-isolation problem in a manner that differs significantly from the traditional and exhaustive failure mode search. System-level diagnosis is based on a functional representation of the system. For example, one can exercise one portion of a radar algorithm (the Fast Fourier Transform (FFT) function) by injecting several standard input patterns and comparing the results to standardized output results. An anomalous output would point to one of several items (including the FFT circuit) without specifying the gate or failure mode. For system-level repair, identifying an anomalous chip is sufficient. We describe here an information theoretic and dependency modeling approach that discards much of the detailed physical knowledge about the system and analyzes its information flow and functional interrelationships. The approach relies on group and flow associations and, as such, is hierarchical. Its hierarchical nature allows the approach to be applicable to any level of complexity and to any repair level. This approach has been incorporated in a product called STAMP (System Testability and Maintenance Program) which was developed and refined through more than 10 years of field-level applications to complex system diagnosis. The results have been outstanding, even spectacular in some cases. In this paper we describe system-level testability, system-level diagnoses, and the STAMP analysis approach, as well as a few STAMP applications.

Simpson, William R.↗

NASA NTRS1993

Cryogenic measurements of aerojet GaAs n-JFETs

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Goebel, John H.↗

NASA NTRS1991

Single phase dynamic CMOS PLA using charge sharing technique

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Dhong, Y. B.↗

NASA NTRS1991

A special purpose silicon compiler for designing supercomputing VLSI systems

Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

Venkateswaran, N.↗

NASA NTRS1993

Design of Center-TRACON Automation System

A system for the automated management and control of terminal area traffic, referred to as the Center-TRACON Automation System (CTAS), is being developed at NASA Ames Research Center. In a cooperative program, NASA and FAA have efforts underway to install and evaluate the system at the Denver area and Dallas/Ft. Worth area air traffic control facilities. This paper will review CTAS architecture, and automation functions as well as the integration of CTAS into the existing operational system. CTAS consists of three types of integrated tools that provide computer-generated advisories for both en-route and terminal area controllers to guide them in managing and controlling arrival traffic efficiently. One tool, the Traffic Management Advisor (TMA), generates runway assignments, landing sequences and landing times for all arriving aircraft, including those originating from nearby feeder airports. TMA also assists in runway configuration control and flow management. Another tool, the Descent Advisor (DA), generates clearances for the en-route controllers handling arrival flows to metering gates. The DA's clearances ensure fuel-efficient and conflict free descents to the metering gates at specified crossing times. In the terminal area, the Final Approach Spacing Tool (FAST) provides heading and speed advisories that help controllers produce an accurately spaced flow of aircraft on the final approach course. Data bases consisting of several hundred aircraft performance models, airline preferred operational procedures, and a three dimensional wind model support the operation of CTAS. The first component of CTAS, the Traffic Management Advisor, is being evaluated at the Denver TRACON and the Denver Air Route Traffic Control Center. The second component, the Final Approach Spacing Tool, will be evaluated in several stages at the Dallas/Fort Worth Airport beginning in October 1993. An initial stage of the Descent Advisor tool is being prepared for testing at the Denver Center in late 1994. Operational evaluations of all three integrated CTAS tools are expected to begin at the two field sites in 1995.

Erzberger, Heinz↗

NASA NTRS1994

Picosecond imaging of sprays

Preliminary results from applying a Kerr-Fourier imaging system to a water/air spray produced by a shear coaxial element are presented. The physics behind ultrafast time-gated optical techniques is discussed briefly. A typical setup of a Kerr-Fourier time gating system is presented.

Breisacher, Kevin↗

NASA NTRS1995

155- and 213-GHz AlInAs/GaInAs/InP HEMT MMIC oscillators

We report on the design and measurement of monolithic 155- and 213-GHz quasi-optical oscillators using AlInAs/GaInAs/InP HEMTs (high-electron mobility transistors). These results are believed to be the highest frequency three-terminal oscillators reported to date. The indium concentration in the channel was 80% for high sheet charge and mobility. The HEMT gates were fabricated with self-aligned sub-tenth-micrometer electron-beam techniques to achieve gate lengths on the order of 50 nm and drain-source spacing of 0.25 micron. Planar antennas were integrated into the fabrication process resulting in a compact and efficient quasi-optical Monolithic Millimeter-wave Integrated Circuit (MMIC) oscillator.

TRT-EXPERIMENTAL↗

NASA NTRS1995

Real time acousto-ultrasonic NDE technique for monitoring damage in ceramic composites under dynamic loads

Research effort was directed towards developing a near real-time, acousto-ultrasonic (AU), nondestructive evaluation (NDE) tool to study the failure mechanisms of ceramic composites. Progression of damage is monitored in real-time by observing the changes in the received AU signal during the actual test. During the real-time AU test, the AU signals are generated and received by the AU transducers attached to the specimen while it is being subjected to increasing quasi-static loads or cyclic loads (10 Hz, R = 1.0). The received AU signals for 64 successive pulses were gated in the time domain (T = 40.96 micro sec) and then averaged every second over ten load cycles and stored in a computer file during fatigue tests. These averaged gated signals are representative of the damage state of the specimen at that point of its fatigue life. This is also the first major attempt in the development and application of real-time AU for continuously monitoring damage accumulation during fatigue without interrupting the test. The present work has verified the capability of the AU technique to assess the damage state in silicon carbide/calcium aluminosilicate (SiC/CAS) and silicon carbide/ magnesium aluminosilicate (SiC/MAS) ceramic composites. Continuous monitoring of damage initiation and progression under quasi-static ramp loading in tension to failure of unidirectional and cross-ply SiC/CAS and quasi-isotropic SiC/MAS ceramic composite specimens at room temperature was accomplished using near real-time AU parameters. The AU technique was shown to be able to detect the stress levels for the onset and saturation of matrix cracks, respectively. The critical cracking stress level is used as a design stress for brittle matrix composites operating at elevated temperatures. The AU technique has found that the critical cracking stress level is 10-15% below the level presently obtained for design purposes from analytical models. An acousto-ultrasonic stress-strain response (AUSSR) model for unidirectional and cross-ply ceramic composites was formulated. The AUSSR model predicts the strain response to increasing stress levels using real-time AU data and classical laminated plate theory. The Weibull parameters of the AUSSR model are used to calculate the design stress for thermo-structural applications. Real-time AU together with the AUSSR model was used to study the failure mechanisms of SiC/CAS ceramic composites under static and fatigue loading. An S-N curve was generated for a cross-ply SiC/CAS ceramic composite material. The AU results are corroborated and complemented by other NDE techniques, namely, in-situ optical microscope video recordings and edge replication.

Tiwari, Anil↗

NASA NTRS1993

A monochromatic gravity wave observed by the Flatland Atmospheric Observatory

On 21 December 1991 from approximately 1300 to approximately 1600 UTC a monochromatic wave train with an 8.2-min period was observed by the suite of instruments at the Flatland Atmospheric Observatory (FAO), located in very flat terrain near Champaign-Urbana, Illinois. A 915-MHz radar measured the vertical wind velocity w every 60 s from 0.55 km MSL (0.34 km AGL) to approximately 3 km with 250-m range gates, and a 50-MHz radar measured the oblique wind in four directions, as well as w, every 130 s from 2.75 to approximately 7.25 km with 750-m range gates. A meteorological ground station measured the surface pressure P, wind speed vector u and azimuth alpha, temperature, solar insolation, etc., every 30 s. P was also measured every 120 s by six digital barograph stations within 30 km of Flatland. Using the hodograph of surface vector u and alpha and the impedance relation, we estimated the azimuthal direction of propagation phi to be 45 deg +/- 15 deg clockwise from north, the intrinsic and apparent horizontal phase speeds C(sub i) and C(sub o), respectively, (which are about equal since the direction of propagation is about normal to the mean wind) to be 21 +/- 5 m/s, and the horizontal wavelength lambda to be 10.0 +/- 2.5 km. The peak-to-peak surface horizontal perturbation velocity varied from approximately 2 to 5 m/s from cycle to cycle.

Vanzandt, T. E.↗

NASA NTRS1995

Airport ramp safety and crew performance issues

This study examined 182 ramp operations incident reports from the Aviation Safety Reporting System (ASRS) database, to determine which factors influence ramp operation incidents. It was found that incidents occurred more often during aircraft arrival operations than during departure operations; incidents occurred most often at the gate stop area, less so at the gate entry/exit areas, and least on the ramp fringe areas; and reporters cited fewer incidents when more ground crew were present. The authors offer suggestions for both airline management and flight crews to reduce the rate of ramp incidents.

Chamberlin, Roy↗

NASA NTRS1996

Low Spillage Metabolic Feeder

An animal feeder for use in a metabolic cage is introduced. The feeder includes a confined passageway and an adjustable notched gate proceeding a food cup. The gate is adjusted so that the entry area to the food cup approximates the cross sectional head area of the animal. Food ejected from the food cup by a caged animal is dropped through a grate into a spill tray.

Evans, JuliAnn↗

NASA NTRS1995

Laser-Induced Incandescence Calibration via Gravimetric Sampling

Various beam imaging and/or sheet forming optics delivered light at 1064 nm from a pulsed Nd:YAG laser for use either as a beam of 3 mm radius or as a laser sheet. Imaging measurements were performed with a grated intensified array camera equipped with an ultraviolet f4.5 lens and a 40 mm extension tube. Point measurements were performed using an ultraviolet 250 mm focal length lens to collect and focus the laser induced incandescence (LII) signal into a 1 meter long quartz optical fiber which directed the LII signal to a 1/4 meter monochromator. An aperture preceding the lens restricted the signal collection region to 1 cm along the laser beam at the center of the gravimetric chimney. Signals from the PMT were processed by a boxcar integrator whereas the images were captured digitally using a frame-grabber with 16 MByte of on-board memory. Both 'point' and planar measurements were made with detector gates of 250 ns to minimize possible morphology bias in collection of the LII signal. Additionally, the imaging measurements were performed with broadband spectral collection of the LII signal to maximize the signal and again minimize any potential effects of morphology dependent heating and/or cooling rates. Digital delay generators controlled the firing of he laser, detector gates and data acquisition. Neutral density filters were used for both sets of measurements to maintain signal levels within linear dynamic ranges of the detectors, the range being determined prior to experiments.

VanderWal, R. L.↗

NASA NTRS1995

A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices

An ultrafast 32-bit pipeline correlator has been implemented using resonant tunneling diodes (RTD) and hetero-junction bipolar transistors (HBT). The negative differential resistance (NDR) characteristics of RTD's is the basis of logic gates with the self-latching property that eliminates pipeline area and delay overheads which limit throughput in conventional technologies. The circuit topology also allows threshold logic functions such as minority/majority to be implemented in a compact manner resulting in reduction of the overall complexity and delay of arbitrary logic circuits. The parallel correlator is an essential component in code division multi-access (CDMA) transceivers used for the continuous calculation of correlation between an incoming data stream and a PN sequence. Simulation results show that a nano-pipelined correlator can provide and effective throughput of one 32-bit correlation every 100 picoseconds, using minimal hardware, with a power dissipation of 1.5 watts. RTD plus HBT based logic gates have been fabricated and the RTD plus HBT based correlator is compared with state of the art complementary metal oxide semiconductor (CMOS) implementations.

Kulkarni, Shriram↗