Results for “processors” — Page 92

NASA NTRSDate not supplied

NASA and Blue Origin’s Flight Assessment of Precision Landing Algorithms Computing Performance

NASA’s Safe and Precise Landing - Integrated Capabilities Evolution (SPLICE) project continues NASA’s work in the development and testing of technologies for Precision Landing and Hazard Avoidance (PL&HA). This paper presents results characterizing how SPLICE flight software utilizes the shared computing resources of the Descent Landing Computer (DLC), one of the PL&HA technologies under development. The SPLICE technologies are being tested as an integrated payload on Blue Origin’s New Shephard suborbital vehicle. The results presented in this paper are measured by applications running in and with the flight software both in flight, and in a high-fidelity Hardware-in-the-Loop (HWIL) simulation environment. Linux utilities to measure performance are also executed from the command line in the HWIL configuration. Performance measurements of the SPLICE workloads executing on the DLC provide insight on how efficiently the software is utilizing the DLC resources. Examples of how these measurements have guided improvements in the flight code are presented. In addition, the DLC uses a commercial processor as a surrogate for NASA’s High Performance Spaceflight Computing (HPSC) processor. This work provides insight on how an HPSC system may perform delivering PL&HA capabilities on a future mission. The measurements also can be used to infer architectural requirements for PL&HA capabilities, informing the HPSC project and other flight computer development efforts. Examples of the measurements collected include processor utilization, I/O bandwidth, cache and branch misses, and application profiles.

Precision Landing and Hazard Avoidance↗

NASA NTRSDate not supplied

Signal and Power Integrity Design Methodology for High-Performance Flight Computing Systems

Computing capabilities of space systems have in-creased onboard performance by orders of magnitude with the use of radiation-tolerant field-programmable gate arrays (FPGA)and processors. The incorporation of signal and power integrity analysis with printed circuit board (PCB) design in reliable computing architectures for space systems has become critical to enable future mission capabilities. Developers launch high-performance processors into a breadth of orbits and missions, running varying applications that create challenges for designing reliable computing hardware. Specifically, for these designs, academic and industry research has focused on component radiation performance, fault mitigation, and reliable architectures. How-ever, other design parameters including electromagnetic interference (EMI), PCB stackup, signal integrity (SI), voltage regulator module (VRM) design, and power distribution network (PDN)are often deprioritized or disregarded as the design matures. Since these characteristics are becoming more significant in high-performance processor designs, this research presents a hardware design and analysis methodology for high-performance, space-computing systems that focuses on a holistic design approach and PDN reliability. While these challenges exist across all space hardware, the reduced PCB dimensions imposed by SmallSats and CubeSats introduce additional hurdles, specifically to VRM and decoupling design. By examining the relationship between the PDN and radiation performance, an analytical relationship is developed that incorporates Total Ionizing Dose and Single-Event Transients to ensure reliability throughout the mission duration. The presented design methodology is applied to the SpaceCube v3.0 Mini, an FPGA-based on-board science data processing system developed at NASA Goddard Space Flight Center.

Advanced avionics↗

NASA NTRSDate not supplied

NASA and Blue Origin’s Flight Assessment of Precision Landing Algorithms Computing Performance

NASA’s Safe and Precise Landing - Integrated Capabilities Evolution (SPLICE) project continues NASA’s work in the development and testing of technologies for Precision Landing and Hazard Avoidance (PL&HA). This paper presents results characterizing how SPLICE flight software utilizes the shared computing resources of the Descent Landing Computer (DLC), one of the PL&HA technologies under development. The SPLICE technologies are being tested as an integrated payload on Blue Origin’s New Shepard suborbital vehicle. The results presented in this paper are measured by applications running in and with the flight software both in flight, and in a high-fidelity Hardware-in-the-Loop (HWIL) simulation environment. Linux utilities to measure performance are also executed from the command line in the HWIL configuration. Performance measurements of the SPLICE workloads executing on the DLC provide insight on how efficiently the software is utilizing the DLC resources. Examples of how these measurements have guided improvements in the flight code are presented. In addition, the DLC uses a commercial processor as a surrogate for NASA’s High-Performance Spaceflight Computing (HPSC) processor. This work provides insight on how an HPSC system may perform delivering PL&HA capabilities on a future mission. The measurements also can be used to infer architectural requirements for PL&HA capabilities, informing the HPSC project and other flight computer development efforts. Examples of the measurements collected include processor utilization, I/O bandwidth, cache and branch misses, and application profiles.

Precision Landing↗

NASA NTRS2023

Development of Two High-Energy Bus ‘Cores’ for Rapid Support of Low-TRL and Educational Payloads: A Software-Configured EPS Combined with Flexible C&DH

For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.

Spacecraft↗

NASA NTRSDate not supplied

Development of Two High-Energy Bus ‘Cores’ for Rapid Support of Low-TRL and Educational Payloads: A Software-Configured EPS Combined with Flexible C&DH

For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.

Spacecraft↗

NASA NTRSDate not supplied

Development of Two High-Energy Bus ‘Cores’

For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.

Avery Brock↗

NASA NTRSDate not supplied

Status of ISS Water Management and Recovery

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment as of March 2023 and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA), Urine Processor Assembly (UPA), and Brine Processor Assembly (BPA).

Jill Williamson↗

NASA NTRS2023

Assessment of the Performance of the Atmospheric Correction Algorithm MAJA for Sentinel-2 Surface Reflectance Estimates

The correction of atmospheric effects on optical remote sensing products is an essential component of Analysis Ready Data (ARD) production lines. The MAJA processor aims at providing accurate time series of surface reflectances over land for satellite missions, such as Sentinel-2, Venμs, and Landsat 8. The Centre d’Études Spatiales de la Biosphère (CESBIO) and the Centre National d’Études Spatiales (CNES) share a common effort to maintain, validate, and improve the MAJA processor, using state-of-the-art ground measurement sites, and participating in processor inter-comparisons, such as the Atmospheric Correction Intercomparison Exercise (ACIX). While contributing to the second ACIX-II Land validation exercise, it was found that the candidate MAJA dataset could not adequately be compared to the main reference dataset. MAJA reflectances were corrected for adjacency and topography effects while the reference dataset was not, excluding MAJA from a part of the performance metrics of the exercise. The first part of the following study aims at providing complementary performance assessment to ACIX-II by reprocessing MAJA surface reflectances without adjacency nor topographic correction, allowing for an un-biased full resolution comparison with the reference Sentinel-2 dataset. The second part of the study consists of validating MAJA against surface reflectance measurements time series of up to five years acquired at three automated stations. Both approaches provide extensive insights on the quality of MAJA Sentinel-2 Level 2 products.

ROSAS↗

NASA NTRSDate not supplied

Onboard Autonomous Trajectory Planning for Mars Power Descent

In recent years, there has been an increasing interest in space-qualified processors such as multi-core central processing units and graphics processing units that can withstand the adverse effects of space radiation. These processors can allow parallel programming to perform tasks that typically demand high computational power. One can study guidance schemes that can take advantage of these currently developing processors and provide more robust guidance. Software for Multi-model Autonomous Real-time Trajectories (SMART) guidance can identify robust trajectories by running an onboard Monte Carlo analysis. SMART guidance can take advantage of knowledge updates obtained from the onboard sensors, allowing it to consider the off-nominal cases that it would not typically encounter during the offline trajectory analysis. This work uses the SMART guidance for the powered divert at Mars simulation in Program to Optimize and Simulated Trajectories- II.

Pardha Sai Chadalavada↗

NASA NTRSDate not supplied

Onboard Autonomous Trajectory Planning for Mars Power Descent

In recent years, there has been an increasing interest in space-qualified processors such as multi-core central processing units and graphics processing units that can withstand the adverse effects of space radiation. These processors can allow parallel programming to perform tasks that typically demand high computational power. One can study guidance schemes that can take advantage of these currently developing processors and provide more robust guidance. Software for Multi-model Autonomous Real-time Trajectories (SMART) guidance can identify robust trajectories by running an onboard Monte Carlo analysis. SMART guidance can take advantage of knowledge updates obtained from the onboard sensors, allowing it to consider the off-nominal cases that it would not typically encounter during the offline trajectory analysis. This work uses the SMART guidance for the powered divert at Mars simulation in Program to Optimize and Simulated Trajectories- II.

Autonomous Planning↗

DOE OSTI2019

Real time feedback-based optimization of distributed energy resources

An example device includes a processor configured to receive a plurality of voltage values corresponding to voltage nodes in a first portion of a power system and determine, for each voltage node, a respective value of first and second voltage-constraint coefficients. The processor is also configured to receive a power value corresponding to a connection point of the first portion of the power system with a second portion of the power system and determine for the connection point, a respective value of first and second power-constraint coefficients. The processor is also configured to cause at least one energy resource connected to the first portion of the power system to modify an output power of the at least one energy resource based on the value of the first and second voltage-constraint coefficients for each voltage node and the value of the first and second power-constraint coefficients.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2020

Dynamically adapting mechanism for translation lookaside buffer shootdowns

An operating system (OS) of a processing system having a plurality of processor cores determines a cost associated with different mechanisms for performing a translation lookaside buffer (TLB) shootdown in response to, for example, a virtual address being remapped to a new physical address, and selects a TLB shootdown mechanism to purge outdated or invalid address translations from the TLB based on the determined cost. In some embodiments, the OS selects an inter-processor interrupt (IPI) as the TLB shootdown mechanism if the cost associated with sending an IPI is less than a threshold cost. In some embodiments, the OS compares the cost of using an IPI as the TLB shootdown mechanism versus the cost of sending a hardware broadcast to all processor cores of the processing system as the shootdown mechanism and selects the shootdown mechanism having the lower cost.

42 ENGINEERING↗

DOE OSTI2020

Constructing a conforming Voronoi mesh for an arbitrarily-shaped enclosed geometric domain

A computing system is described herein, where the computing system includes a processor and memory storing instructions that, when executed by the processor, cause the processor to perform the following acts: 1) receiving a computer-implemented definition of an enclosed geometric domain, wherein the geometric domain is two-dimensional; 2) determining locations of seeds for the enclosed geometric domain; 3) decomposing the enclosed geometric domain into a conforming Voronoi mesh based on the locations of the seeds, wherein the conforming Voronoi mesh comprises Voronoi cells, and further wherein the conforming Voronoi mesh is bounded by the enclosed domain; and 4) performing a numerical simulation to generate simulation results, wherein the numerical simulation is based on at least one Voronoi cell in the Voronoi cells of the conforming Voronoi mesh.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Constructing a conforming voronoi mesh for an arbitrarily-shaped enclosed geometric domain

A computing system is described herein, where the computing system includes a processor and memory storing instructions that, when executed by the processor, cause the processor to perform the following acts: 1) receiving a computer-implemented definition of an enclosed geometric domain, wherein the geometric domain is three-dimensional; 2) determining locations of seeds for the enclosed geometric domain; 3) decomposing the enclosed geometric domain into a conforming Voronoi mesh based on the locations of the seeds, wherein the conforming Voronoi mesh comprises Voronoi cells, and further wherein the conforming Voronoi mesh is bounded by the enclosed domain; and 4) performing a numerical simulation to generate simulation results, wherein the numerical simulation is based on at least one Voronoi cell in the Voronoi cells of the conforming Voronoi mesh.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Device and method for cache utilization aware data compression

A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.

Das, Shomit N.↗

DOE OSTI2021

Real time feedback-based optimization of distributed energy resources

An example device includes a processor configured to receive a plurality of voltage values representing respective voltage magnitudes at voltage nodes in a first portion of a power system and determine, for each voltage node, a respective value of first and second voltage-constraint coefficients. The processor is also configured to receive a power value corresponding to a connection point of the first portion of the power system with a second portion of the power system and determine for the connection point, a respective value of first and second power-constraint coefficients. The processor is also configured to cause at least one energy resource connected to the first portion of the power system to modify an output power of the at least one energy resource based on the value of the first and second voltage-constraint coefficients for each voltage node and the value of the first and second power-constraint coefficients.

Dall'Anese, Emiliano↗

DOE OSTI2021

Hardware accelerated dynamic work creation on a graphics processing unit

A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Gutierrez, Anthony↗

DOE OSTI2021

Bringing OpenCL to Commodity RISC-V CPUs

The importance of open-source hardware has been increasing in recent years with the introduction of the RISC-V Open ISA. This has also accelerated the push for support of the open-source software stack from compiler tools to full-blown operating systems. Parallel computing with today’s Application Programming Interfaces such as OpenCL has proven to be effective at leveraging the parallelism in commodity multi-core processors and programmable parallel accelerators. However, to the best of our knowledge, there is currently no publicly available implementation of OpenCL targeting commodity RISC-V processors that is accessible to the open-source community. Besides opening RISC-V to the existing rich variety of scientific parallel applications, OpenCL also provides access to a unique genre of benchmarks useful in computer architecture research. In this work, we extended an Open-source implementation of OpenCL to target RISC-V CPUs. Our work not only cover commodity multi-core RISC-V processors, but also plethora of low- profile embedded RISC-V CPUs that often do not support atomic instructions or multi-threading.

Tine, Blaise↗