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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,657 records · Page 92
All sourcesNASA NTRSDOE OSTI
NASA NTRS1982

Electrically reconfigurable logic array

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

Agarwal, R. K.↗
NASA NTRS1983

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

Strohkorb, G. A.↗
NASA NTRS1983

Data highway terminal controller

A data highway terminal controller with transmission controllers assigned to each processor in a set of multiple processors is described. Shared-use terminals are loop connected to the processors via the controllers.

Yoshimoto, T.↗
NASA NTRS1982

Geology and image processing

Digital image processing for geological applications will be integrated with geographic information systems and data base management systems. While multiband data sets from radar and multispectral scanners will make extreme demands on memory, bus and processor architectures, it is expected that array processors and VLSI/VHSIC dedicated function chips will allow the use of fast Fourier transform and classification algorithms. It is anticipted that, as processor power increases, the weakest link of a processing system will become the analyst who uses it. Human engineering of systems is therefore recommended for the most effective utilization of remotely sensed geologic data.

Daily, M.↗
NASA NTRS1983

Simplified power processing for ion-thruster subsystems

A review of the thruster/power-processor-interface requirements for (mercury and inert gas) ion-thrusters, an evaluation of various approaches to simplifying the power-processor circuitry, and the test results of the recently developed 8-cm mercury-ion-thruster simplified power-processor unit (SPPU) are presented. The SPPU demonstrates the feasibility of stable thruster operation using highly simplified power-processing techniques and achieves an approximately tenfold reduction in the electronic parts count when compared to the existing power-processor unit (PPU) used in the Hughes/NASA Lewis Research Center 8-cm-diameter (mercury) Ion Auxiliary Propulsion Subsystem (IAPS).

Wessel, F. J.↗
NASA NTRS1982

Onboard processing for a 30/20 GHz communications satellite

A systems configuration for the baseband processor for a TDMA communications satellite utilizing the 30 GHz uplink and 20 GHz downlink bands will be discussed. The baseband processor functions include QPSK burst demodulation, convolutional decoding, data routing, encoding, QPSK modulation, and antenna steering. The performance of the burst demodulator will be examined. Power and weight estimates for the baseband processor will be presented.

Reisenfeld, S.↗
NASA NTRS1983

A sun acquisition sensor for spacecraft guidance and control

The combination of a strap-down analog sun acquisition sensor (AS) and an on-board digital programmable signal processor results in a versatile guidance and control system. The combination can orient the rotation axis of a spin-stabilized spacecraft to the sun no matter what the initial attitude of the spacecraft. During the sun orientation process, spacecraft spin rate can be sensed and supplied as an input to the control algorithm. If needed, the AS-signal processor combination can be used to perform a rhumb-line turn maneuver. In case of unexpected spacecraft operating conditions, or unplanned pointing directions, the signal processor program can be updated via earth-based transmission of another program to cover the new situation. Using only three radiation-hard cadmium-sulfide detectors, containing no moving parts, needing only a few microwatts of power, included in a volume of 550 cubic cm (a redundant pair), and weighing only 540 grams, the AS is a small, simple, sturdy sensing device.

Birnbaum, M. M.↗
NASA NTRS1984

Optical systolic solutions of linear algebraic equations

The philosophy and data encoding possible in systolic array optical processor (SAOP) were reviewed. The multitude of linear algebraic operations achievable on this architecture is examined. These operations include such linear algebraic algorithms as: matrix-decomposition, direct and indirect solutions, implicit and explicit methods for partial differential equations, eigenvalue and eigenvector calculations, and singular value decomposition. This architecture can be utilized to realize general techniques for solving matrix linear and nonlinear algebraic equations, least mean square error solutions, FIR filters, and nested-loop algorithms for control engineering applications. The data flow and pipelining of operations, design of parallel algorithms and flexible architectures, application of these architectures to computationally intensive physical problems, error source modeling of optical processors, and matching of the computational needs of practical engineering problems to the capabilities of optical processors are emphasized.

Neuman, C. P.↗
NASA NTRS1984

Systolic triple-matrix product calculations

In order to handle arbitrary-sized matrices with fixed-sized optical matrix processors, it is necessary to expand or contract the problem to fit the processor. This preprocessing is examined. It is applied to the type of triple-matrix product calculation needed for Kalman filtering. Emphasis will be placed on systolic-type processors.

Caulfield, H. J.↗
NASA NTRS1983

Implicit, nonswitching, vector-oriented algorithm for steady transonic flow

A rapid computation of a sequence of transonic flow solutions has to be performed in many areas of aerodynamic technology. The employment of low-cost vector array processors makes the conduction of such calculations economically feasible. However, for a full utilization of the new hardware, the developed algorithms must take advantage of the special characteristics of the vector array processor. The present investigation has the objective to develop an efficient algorithm for solving transonic flow problems governed by mixed partial differential equations on an array processor.

Lottati, I.↗
NASA NTRS1983

Synthetic aperture radar imaging using acousto-optics and charge-coupled devices

The operating principles of an acoustooptic/CCD real-time SAR processor are described, and experimental results are presented. Particular consideration is given to time-and-space integrating processing, the range processor, and the azimuth processor. The interferometric detection scheme is examined in detail.

Psaltis, D.↗
NASA NTRS1982

Output statistics of laser anemometers in sparsely seeded flows

It is noted that until very recently, research on this topic concentrated on the particle arrival statistics and the influence of the optical parameters on them. Little attention has been paid to the influence of subsequent processing on the measurement statistics. There is also controversy over whether the effects of the particle statistics can be measured. It is shown here that some of the confusion derives from a lack of understanding of the experimental parameters that are to be controlled or known. A rigorous framework is presented for examining the measurement statistics of such systems. To provide examples, two problems are then addressed. The first has to do with a sample and hold processor, the second with what is called a saturable processor. The sample and hold processor converts the output to a continuous signal by holding the last reading until a new one is obtained. The saturable system is one where the maximum processable rate is arrived at by the dead time of some unit in the system. At high particle rates, the processed rate is determined through the dead time.

Edwards, R. V.↗
NASA NTRS1984

Optical Kalman filtering for missile guidance

Optical systolic array processors constitute a powerful and general-purpose set of optical architectures with high computational rates. In this paper, Kalman filtering, a novel application for these architectures, is investigated. All required operations are detailed; their realization by optical and special-purpose analog electronics are specified; and the processing time of the system is quantified. The specific Kalman filter application chosen is for an air-to-air missile guidance controller. The architecture realized in this paper meets the design goal of a fully adaptive Kalman filter which processes a measurement every 1 msec. The vital issue of flow and pipelining of data and operations in a systolic array processor is addressed. The approach is sufficiently general and can be realized on an optical or digital systolic array processor.

Casasent, D.↗
NASA NTRS1984

The FLEX/32 multicomputing environment

The FLEX/32 Multicomputer is a generic environment for cooperating multiple processors. The FLEX/32 supports a number of different processors, making it heterogeneous in terms of the instruction sets it supports, and homogeneous in its ability to provide consistent storage and input/output facilities to its differing processors. These facilities are accessed through standard 32-bit VMEbus connections. The FLEX/32 supports the full UNIX System V Operating System and languages associated with it, plus the extended ConCurrent C and Concurrent FORTRAN 77 languages that allow programming of concurrent software at a high level. Direct programming support at all levels is provided by the environment hardware for concurrent software execution and optimization, including hardware support for shared resource access arbitration, conditional critical region arbitration, and interprocessor messages.

Matelan, N.↗
NASA NTRS1985

SPAR improved structural-fluid dynamic analysis capability

The results of a study whose objective was to improve the operation of the SPAR computer code by improving efficiency, user features, and documentation is presented. Additional capability was added to the SPAR arithmetic utility system, including trigonometric functions, numerical integration, interpolation, and matrix combinations. Improvements were made in the EIG processor. A processor was created to compute and store principal stresses in table-format data sets. An additional capability was developed and incorporated into the plot processor which permits plotting directly from table-format data sets. Documentation of all these features is provided in the form of updates to the SPAR users manual.

Pearson, M. L.↗
NASA NTRS1984

Landsat image registration - A study of system parameters

Some applications of Landsat data, particularily agricultural and forestry applications, require the ability to geometrically superimpose or register data acquired at different times and possibly by different satellites. An experimental investigation relating to a registration processor used by the Johnson Space Center for this purpose is the subject of this paper. Correlation of small subareas of images is at the heart of this registration processor and the manner in which various system parameters affect the correlation process is the prime area of investigation. Parameters investigated include preprocessing methods, methods for detecting sucessful correlations, fitting a surface to the correlation patch, fraction of pixels designated as edge pixels in edge detection adn local versus global generation of edge images. A suboptimum search procedure is used to find a good parameter set for this registration processor.

Wacker, A. G.↗
NASA NTRS1985

Moving target, distributed, real-time simulation using Ada

Research on a precompiler solution is described for the moving target compiler problem encountered when trying to run parallel simulation algorithms on several microcomputers. The precompiler is under development at NASA-Lewis for simulating jet engines. Since the behavior of any component of a jet engine, e.g., the fan inlet, rear duct, forward sensor, etc., depends on the previous behaviors and not the current behaviors of other components, the behaviors can be modeled on different processors provided the outputs of the processors reach other processors in appropriate time intervals. The simulator works in compute and transfer modes. The Ada procedure sets for the behaviors of different components are divided up and routed by the precompiler, which essentially receives a multitasking program. The subroutines are synchronized after each computation cycle.

Collins, W. R.↗