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NASA NTRS1985

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.

Jones, C. W.↗
NASA NTRS1986

Ka-band monolithic gain control amplifier

A monolithic gain control amplifier for Ka-band has been developed based on 0.25 micron-gate-length dual-gate FETs fabricated on ion-implanted material. A single-stage monolithic amplifier gives a gain of 6 dB at 31 GHz including fixture losses with a gain control range of over 20 dB. The device and IC design and fabrication are described.

Geddes, J.↗
NASA NTRS1984

The 20 GHz GaAs monolithic power amplifier module development

The development of a 20 GHz GaAs FET monlithic power amplifier module for advanced communication applications is described. Four-way power combing of four 0.6 W amplifier modules is used as the baseline approach. For this purpose, a monolithic four-way traveling-wave power divider/combiner was developed. Over a 20 GHz bandwidth (10 to 30 GHz), an insertion loss of no more than 1.2 dB was measured for a pair of back-to-back connected divider/combiners. Isolation between output ports is better than 20 dB, and VSWRs are better than 21:1. A distributed amplifier with six 300 micron gate width FETs and gate and drain transmission line tapers has been designed, fabricated, and evaluated for use as an 0.6 W module. This amplifier has achieved state-of-the-art results of 0.5 W output power with at least 4 dB gain across the entire 2 to 21 GHz frequency range. An output power of 2 W was achieved at a measurement frequency of 18 GHz when four distributed amplifiers were power-combined using a pair of traveling-wave divider/combiners. Another approach is the direct common-source cascading of three power FET stages. An output power of up to 2W with 12 dB gain and 20% power-added efficiency has been achieved with this approach (at 17 GHz). The linear gain was 14 dB at 1 W output. The first two stages of the three-stage amplifier have achieved an output power of 1.6 W with 9 dB gain and 26% power-added efficiency at 16 GHz.

Source record↗
NASA NTRS1987

The fault-tree compiler

The Fault Tree Compiler Program is a new reliability tool used to predict the top event probability for a fault tree. Five different gate types are allowed in the fault tree: AND, OR, EXCLUSIVE OR, INVERT, and M OF N gates. The high level input language is easy to understand and use when describing the system tree. In addition, the use of the hierarchical fault tree capability can simplify the tree description and decrease program execution time. The current solution technique provides an answer precise (within the limits of double precision floating point arithmetic) to the five digits in the answer. The user may vary one failure rate or failure probability over a range of values and plot the results for sensitivity analyses. The solution technique is implemented in FORTRAN; the remaining program code is implemented in Pascal. The program is written to run on a Digital Corporation VAX with the VMS operation system.

Martensen, Anna L.↗
NASA NTRS1986

Low-noise behavior of InGaAs quantum-well-structured modulation-doped FET's from 10 to the -2nd to 10 to the 8 Hz

Equivalent gate noise voltage spectra of 1-micron gate-length modulation-doped FET's with pseudomorphic InGaAs quantum-well structure have been measured for the frequency range of 0.01 Hz to 100 MHz and commpared with the noise spectra of conventional AlGaAs/GaAs MODFET's and GaAs MESFET's. The prominent generation-recombination (g-r) noise bulge commonly observed in the vicinity of 10 kHz in conventional MODFET's at 300 K does not appear in the case of the new InGaAs quantum-well MODFET. Instead, its noise spectra indicate the presence of low-intensity multiple g-r noise components superimposed on a reduced 1/f noise. The LF noise intensity in the new device appears to be the lowest among those observed in any MODFET or MESFET. The noise spectra at 82 K in the new device represent nearly true 1/f noise. This unusual low-noise behavior of the new structure suggests the effectiveness of electron confinement in the quantum well that significantaly reduces electron trapping in the n-AlGaAs, and thus eliminates the g-r noise bulge observed in conventional MODFET's.

Liu, Shih-Ming J.↗
NASA NTRS1987

Response of a metal-oxide-semiconductor field-effect transistor to a cosmic-ray ion track

A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.

Benumof, Reuben↗
NASA NTRS1986

Possible effects of organelle charge and density on cell metabolism

A system of perception and transduction involving the gravity-induced asymmetric distribution of a plant growth hormone is studied. A theory is constructed which assumes that the perception of the gravitational stimulus involved a perturbation of the plant's bioelectric field and that the transduction of the stimulus involved voltage-gating of hormone movement from the plant's vascular tissue into the hormone responsive growing tissue. Particular attention is focused on the barriers to indole-3-acetic acid (IAA) transport from the seed to the mesocotyl cortex, the protoinhibition of IAA movement from the endosperm to the shoot, the effects of the gravitational stimulus on the movement of IAA from the kernel to the shoot, electrochemical gating as a target for the gravity stimulus, and the gravity sensing mechanism.

Bandurski, Robert S.↗
NASA NTRS1986

Satellite rainfall retrieval by logistic regression

The potential use of logistic regression in rainfall estimation from satellite measurements is investigated. Satellite measurements provide covariate information in terms of radiances from different remote sensors.The logistic regression technique can effectively accommodate many covariates and test their significance in the estimation. The outcome from the logistical model is the probability that the rainrate of a satellite pixel is above a certain threshold. By varying the thresholds, a rainrate histogram can be obtained, from which the mean and the variant can be estimated. A logistical model is developed and applied to rainfall data collected during GATE, using as covariates the fractional rain area and a radiance measurement which is deduced from a microwave temperature-rainrate relation. It is demonstrated that the fractional rain area is an important covariate in the model, consistent with the use of the so-called Area Time Integral in estimating total rain volume in other studies. To calibrate the logistical model, simulated rain fields generated by rainfield models with prescribed parameters are needed. A stringent test of the logistical model is its ability to recover the prescribed parameters of simulated rain fields. A rain field simulation model which preserves the fractional rain area and lognormality of rainrates as found in GATE is developed. A stochastic regression model of branching and immigration whose solutions are lognormally distributed in some asymptotic limits has also been developed.

Chiu, Long S.↗
NASA NTRS1989

Coolant-Control Valves For Fluid-Sampling Probes

Small built-in leaks prevent overheating. Downstream flow-control globe valve replaced with modified gate valve. Modification consists of drilling small hole through valve gate, so valve never turned completely off. This "leaky" valve provides enough flow of coolant to prevent overheating causing probe to fail. Principle also applied to automatic control system by installing small bypass line around control valve.

Schultz, Donald F.↗
NASA NTRS1989

Single Electrode Would Control Charge-Coupled Device

Space saved and interelectrode short circuits eliminated. Proposed virtual-phase, interline-transfer, charge-couple device uses single gate electrode to control both interline and intraline transfer of charge. Voltage on single control electrode varied to transfer charge from photosites to shift register, or else along sift register. Two kinds of transfer independent of each other. Charge transferred along shift register when voltage on control electrode alternated between gate potentials.

Wadsworth, Mark↗
NASA NTRS1989

Impact of device level faults in a digital avionic processor

This study describes an experimental analysis of the impact of gate and device-level faults in the processor of a Bendix BDX-930 flight control system. Via mixed mode simulation, faults were injected at the gate (stuck-at) and at the transistor levels and, their propagation through the chip to the output pins was measured. The results show that there is little correspondence between a stuck-at and a device-level fault model, as far as error activity or detection within a functional unit is concerned. In so far as error activity outside the injected unit and at the output pins are concerned, the stuck-at and device models track each other. The stuck-at model, however, overestimates, by over 100 percent, the probability of fault propagation to the output pins. An evaluation of the Mean Error Durations and the Mean Time Between Errors at the output pins shows that the stuck-at model significantly underestimates (by 62 percent) the impact of an internal chip fault on the output pins. Finally, the study also quantifies the impact of device fault by location, both internally and at the output pins.

Suk, Ho Kim↗
NASA NTRS1989

The Fault Tree Compiler (FTC): Program and mathematics

The Fault Tree Compiler Program is a new reliability tool used to predict the top-event probability for a fault tree. Five different gate types are allowed in the fault tree: AND, OR, EXCLUSIVE OR, INVERT, AND m OF n gates. The high-level input language is easy to understand and use when describing the system tree. In addition, the use of the hierarchical fault tree capability can simplify the tree description and decrease program execution time. The current solution technique provides an answer precisely (within the limits of double precision floating point arithmetic) within a user specified number of digits accuracy. The user may vary one failure rate or failure probability over a range of values and plot the results for sensitivity analyses. The solution technique is implemented in FORTRAN; the remaining program code is implemented in Pascal. The program is written to run on a Digital Equipment Corporation (DEC) VAX computer with the VMS operation system.

Butler, Ricky W.↗
NASA NTRS1989

Paralleling power MOSFETs in their active region: Extended range of passively forced current sharing

A simple passive circuit that improves current balance in parallelled power MOSFETs that are not precisely matched and that are operated in their active region from a common gate drive are exhibited. A nonlinear circuit consisting of diodes and resistors generates the differential gate potential required to correct for unbalance while maintaining low losses over a range of current. Also application of a thin tape wound magnetic core to effect dynamic current balance is reviewed, and a simple theory is presented showing that for operation in the active region the branch currents tend to revert to their normal unbalanced values even if the core is not driven into saturation. Results of several comparative experiments are given.

Niedra, Janis M.↗
NASA NTRS1988

GaAs circuits for monolithic optical controller

GaAs circuits for use in a fully monolithic 1 Gb/s optical controller have been developed and tested. The circuits include photodetectors, transimpedance amplifiers and 1:16 demultiplexers that can directly control the phase of MMIC phase shifters. The entire chip contains approximately 300 self-aligned gate E/D-mode MESFETs. The MESFETs have one micron-wide gate and the E-mode FETs typically have transconductance of 200 ms/mm. Results of simulations and tests are reported. Also, the design and layout of the fully monolithic chip is discussed.

Gustafson, G.↗
NASA NTRS1988

Impact of device level faults in a digital avionic processor

This paper describes an experimental analysis of the impact of gate and device-level faults in the processor of a flight control system. Via mixed mode simulation faults were injected both at the gate (stuck-at) and at the transistor levels, and their propagation through the chip to the output pins was measured. The results show that there is little correspondence between a stuck-at and a device-level fault model insofar as error activity or detection within a functional unit is concerned. Insofar as error activity outside the injected unit and at the output pins are concerned, the stuck-at and device models track each other, although the stuck-at model overestimates, by over one hundred percent, the probability of fault propagation to the output pins. The stuck-at model significantly underestimates the impact of an internal chip fault on the output pins.

Kim, S.↗
NASA NTRS1988

High-performance Ka-band and V-band HEMT low-noise amplifiers

Quarter-micron-gate-length high-electron-mobility transistors (HEMTs) have exhibited state-of-the-art low-noise performance at millimeter-wave frequencies, with minimum noise figures of 1.2 dB at 32 GHz and 1.8 dB at 60 GHz. At Ka-band, two-stage and three-stage HEMT low noise amplifiers have demonstrated noise figures of 1.7 and 1.9 dB, respectively, with associated gains of 17.0 and 24.0 dB at 32 GHz. At V-band, two stage and three-stage HEMT amplifiers yielded noise figures of 3.2 and 3.6 dB, respectively, with associated gains of 12.7 and 20.0 dB at 60 GHz. The 1-dB-gain compression point of all the amplifiers is greater than +6 dBm. The results clearly show the potential of short-gate-length HEMTs for high-performance millimeter-wave receiver applications.

Duh, K. H. George↗
NASA NTRS1988

Simulation and measurement of disturbance propagation in a single tether system

One of the missions of the Getaway Tether Experiment (GATE) is to investigate disturbance propagation and control in a tethered system. In order to understand the nature of the propagation, simulation of the tether response is vital. A single finite duration pulse is the source of the disturbance. A bead model is used to predict the motion of the tether and the end masses (modeled as point masses). System response is checked for different magnitudes of force and for different points of impact on the tether. Along with simulation, hardware development is needed, especially in the area of tension measurement. At this time, hardware is being developed to measure the tension in the tether, so that the tethered system can be controlled via tension feedback. The hardware will then be tested in conjunction with the Dynamics and Control Mission of the GATE project.

Greene, Michael↗
NASA NTRS1988

Ka-band MMIC beam steered transmitter array

A 32 GHz six element linear transmitter array which employs MMIC phase shifters and power amplifiers is developed and its performance is evaluated. The MMIC phase shifters contains 14 MESFETs in three digital switched line and one analog loaded line phase shifter, and the MMIC power amplifiers are two stage amplifiers using GaAs MESFETs with 0.25 micron gate lengths and gate widths of 0.1 mm and 0.3 mm. The design of the array is described. The phase shift measurements for the MMIC devices are analyzed. The data reveal that the switched line phase shifters are accurate to within 7 pct; the power amplifier 1 dB compressed output power varied over 0.3 dB; the beamwidth of the array is 7.5 deg; and beam steering is over + or - 8 deg.

Riley, A. L.↗