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At least 1,639 records · Page 91
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Compact Low-Loss Planar Magic-T

This design allows broadband power combining with high isolation between the H port and E port, and achieves a lower insertion loss than any other broadband planar magic-T. Passive micro wave/millimeter-wave signal power is combined both in-phase and out-of-phase at the ports, with the phase error being less than 1 , which is limited by port impedance. The in-phase signal combiner consists of two quarter-wavelength-long transmission lines combined at the microstrip line junction. The out-of-phase signal combiner consists of two half-wavelength-long transmission lines combined in series. Structural symmetry creates a virtual ground plane at the combining junction, and the combined signal is converted from microstrip line to slotline. Optimum realizable characteristic impedances are used so that the magic-T provides broadband response with low return loss. The magic-T is used in microwave and millimeter-wave frequencies, with the operating bandwidth being approximately 100 percent. The minimum isolation obtainable is 32 dB from port E to port H. The magic-T VSWR is less than 1.1 in the operating band. Operating temperature is mainly dependent on the variation in the dielectric constant of the substrate. Using crystallized substrate, the invention can operate in an extremely broad range of temperatures (from 0 to 400 K). It has a very high reliability because it has no moving parts and requires no maintenance, though it is desirable that the magic-T operate in a low-humidity environment. Fabrication of this design is very simple, using only two metallized layers. No bond wires, via holes, or air bridges are required. Additionally, this magic-T can operate as an individual component without auxiliary components.

U-yen, Kongpop↗
NASA NTRS2008

Thermally Driven Josephson Effect

A concept is proposed of the thermally driven Josephson effect in superfluid helium. Heretofore, the Josephson effect in a superfluid has been recognized as an oscillatory flow that arises in response to a steady pressure difference between two superfluid reservoirs separated by an array of submicron-sized orifices, which act in unison as a single Josephson junction. Analogously, the thermally driven Josephson effect is an oscillatory flow that arises in response to a steady temperature difference. The thermally driven Josephson effect is partly a consequence of a quantum- mechanical effect known as the fountain effect, in which a temperature difference in a superfluid is accompanied by a pressure difference. The thermally driven Josephson effect may have significance for the development of a high-resolution gyroscope based on the Josephson effect in a superfluid: If the pressure-driven Josephson effect were used, then the fluid on the high-pressure side would become depleted, necessitating periodic interruption of operation to reverse the pressure difference. If the thermally driven Josephson effect were used, there would be no net flow and so the oscillatory flow could be maintained indefinitely by maintaining the required slightly different temperatures on both sides of the junction.

Penanen, Konstantin↗
NASA NTRS2009

In-Phase Power-Combined Frequency Tripler at 300 GHz

This design starts with commercial 85- to 115-GHz sources that are amplified to as much as 250 mW using power amplifiers developed for the Herschel Space Observatory. The frequency is then tripled using a novel waveguide GaAs Schottky diode frequency tripler. This planar diode produces 26 mW at 318 GHz. Peak conversion efficiency is over 15 percent, and the measured bandwidth of about 265 - 30 GHz is limited more by the driving source than by the tripler itself. This innovation is based on an integrated circuit designed originally for a single-chip 260- to 340-GHz balanced tripler. The power-combined version has two mirror-image tripler chips that are power-combined in-phase in a single waveguide block using a compact Y-junction divider at the input waveguide, and a Y-junction combiner at the output waveguide. The tripler uses a split-block waveguide design with two independent DC bias lines.

Maestrini, Alain↗
NASA NTRS2008

Instrumentation System Diagnoses a Thermocouple

An improved self-validating thermocouple (SVT) instrumentation system not only acquires readings from a thermocouple but is also capable of detecting deterioration and a variety of discrete faults in the thermocouple and its lead wires. Prime examples of detectable discrete faults and deterioration include open- and short-circuit conditions and debonding of the thermocouple junction from the object, the temperature of which one seeks to measure. Debonding is the most common cause of errors in thermocouple measurements, but most prior SVT instrumentation systems have not been capable of detecting debonding. The improved SVT instrumentation system includes power circuitry, a cold-junction compensator, signal-conditioning circuitry, pulse-width-modulation (PWM) thermocouple-excitation circuitry, an analog-to-digital converter (ADC), a digital data processor, and a universal serial bus (USB) interface. The system can operate in any of the following three modes: temperature measurement, thermocouple validation, and bonding/debonding detection. The software running in the processor includes components that implement statistical algorithms to evaluate the state of the thermocouple and the instrumentation system. When the power is first turned on, the user can elect to start a diagnosis/ monitoring sequence, in which the PWM is used to estimate the characteristic times corresponding to the correct configuration. The user also has the option of using previous diagnostic values, which are stored in an electrically erasable, programmable read-only memory so that they are available every time the power is turned on.

Perotti, Jose↗
NASA NTRS2009

Power System Mass Analysis for Hydrogen Reduction Oxygen Production on the Lunar Surface

The production of oxygen from the lunar regolith requires both thermal and electrical power in roughly similar proportions. This unique power requirement is unlike most applications on the lunar surface. To efficiently meet these requirements, both solar PV array and solar concentrator systems were evaluated. The mass of various types of photovoltaic and concentrator based systems were calculated to determine the type of power system that provided the highest specific power. These were compared over a range of oxygen production rates. Also a hybrid type power system was also considered. This system utilized a photovoltaic array to produce the electrical power and a concentrator to provide the thermal power. For a single source system the three systems with the highest specific power were a flexible concentrator/Stirling engine system, a rigid concentrator/Stirling engine system and a tracking triple junction solar array system. These systems had specific power values of 43, 34, and 33 W/kg, respectively. The hybrid power system provided much higher specific power values then the single source systems. The best hybrid combinations were the triple junction solar array with the flexible concentrator and the rigid concentrator. These systems had a specific power of 81 and 68 W/kg, respectively.

Colozza, Anthony J.↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
NASA NTRS2007

Toward a III-V Multijunction Space Cell Technology on Si

High efficiency compound semiconductor solar cells grown on Si substrates are of growing interest in the photovoltaics community for both terrestrial and space applications. As a potential substrate for III-V compound photovoltaics, Si has many advantages over traditional Ge and GaAs substrates that include higher thermal conductivity, lower weight, lower material costs, and the potential to leverage the extensive manufacturing base of the Si industry. Such a technology that would retain high solar conversion efficiency at reduced weight and cost would result in space solar cells that simultaneously possess high specific power (W/kg) and high power density (W/m2). For terrestrial solar cells this would result in high efficiency III-V concentrators with improved thermal conductivity, reduced cost, and via the use of SiGe graded interlayers as active component layers the possibility of integrating low bandgap sub-cells that could provide for extremely high conversion efficiency.1 In addition to photovoltaics, there has been an historical interest in III-V/Si integration to provide optical interconnects in Si electronics, which has become of even greater relevance recently due to impending bottlenecks in CMOS based circuitry. As a result, numerous strategies to integrate GaAs with Si have been explored with the primary issue being the approx.4% lattice mismatch between GaAs and Si. Among these efforts, relaxed, compositionally-graded SiGe buffer layers where the substrate lattice constant is effectively tuned from Si to that of Ge so that a close lattice match to subsequent GaAs overlayers have shown great promise. With this approach, threading dislocation densities (TDDs) of approx.1 x 10(exp 6)/sq cm have been uniformly achieved in relaxed Ge layers on Si,5 leading to GaAs on Si with minority carrier lifetimes greater than 10 ns,6 GaAs single junction solar cells on Si with efficiencies greater than 18%,7 InGaAs CW laser diodes on Si,8 and room temperature GaInP red laser diodes on Si.9 Here we report on the first high performance dual junction GaInP/GaAs solar cells grown on Si using this promising SiGe engineered substrate approach.

Ringel, S. A.↗
NASA NTRS2007

Space Solar Cell Research and Development Projects at Emcore Photovoltaics

The GaInP2/InGaAs/Ge triple junction device lattice matched to germanium has achieved the highest power conversion efficiency and the most commercial success for space applications [1]. What are the practical performance limits of this technology? In this paper we will describe what we consider to be the practical performance limits of the lattice matched GaInP2/InGaAs/Ge triple junction cell. In addition, we discuss the options for next generation space cell performance.

Sharps, Paul↗
NASA NTRS2007

Lightweight, Flexible Solar Cells on Stainless Steel Foil and Polymer for Space and Stratospheric Applications

The availability of low-cost, lightweight and reliable photovoltaic (PV) modules is an important component in reducing the cost of satellites and spacecraft. In addition, future high-power spacecraft will require lightweight PV arrays with reduced stowage volume. In terms of the requirements for low mass, reduced stowage volume, and the harsh space environment, thin film amorphous silicon (a-Si) alloy cells have several advantages over other material technologies (1). The deposition process is relatively simple, inexpensive, and applicable to large area, lightweight, flexible substrates. The temperature coefficient has been found to be between -0.2 and -0.3 %/degC for high-efficiency triple-junction a-Si alloy cells, which is superior for high temperature operation compared to crystalline Si and triple-junction GaAs/InGaP/Ge devices at 0.53 %/degC and 0.45 %/degC, respectively (2). As a result, the reduction in efficiency at high temperature typical in space conditions is less for a-Si alloy cells than for their crystalline counterparts. Additionally, the a-Si alloy cells are relatively insensitive to electron and proton bombardment. We have shown that defects that are created by electrons with energies between 0.2 to 2 MeV with fluence up to 1x10(exp 15) e/sq cm and by protons with energy in the range 0.3 MeV to 5 MeV with fluence up to 1x10(exp 13) p/sq cm can be annealed out at 70 C in less than 50 hours (1). Further, modules incorporating United Solar s a-Si alloy cells have been tested on the MIR space station for 19 months with only minimal degradation (3). For stratospheric applications, such as the high altitude airship, the required PV arrays are typically of considerably higher power than current space arrays. Airships typically have a large area available for the PV, but weight is of critical importance. As a result, low cost and high specific power (W/kg) are key factors for airship PV arrays. Again, thin-film a-Si alloy solar cell technology is well suited to such applications.

Beernink, Kevin↗
NASA NTRS2009

Zinc Alloys for the Fabrication of Semiconductor Devices

ZnBeO and ZnCdSeO alloys have been disclosed as materials for the improvement in performance, function, and capability of semiconductor devices. The alloys can be used alone or in combination to form active photonic layers that can emit over a range of wavelength values. Materials with both larger and smaller band gaps would allow for the fabrication of semiconductor heterostructures that have increased function in the ultraviolet (UV) region of the spectrum. ZnO is a wide band-gap material possessing good radiation-resistance properties. It is desirable to modify the energy band gap of ZnO to smaller values than that for ZnO and to larger values than that for ZnO for use in semiconductor devices. A material with band gap energy larger than that of ZnO would allow for the emission at shorter wavelengths for LED (light emitting diode) and LD (laser diode) devices, while a material with band gap energy smaller than that of ZnO would allow for emission at longer wavelengths for LED and LD devices. The amount of Be in the ZnBeO alloy system can be varied to increase the energy bandgap of ZnO to values larger than that of ZnO. The amount of Cd and Se in the ZnCdSeO alloy system can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped or can be p-type doped using selected dopant elements, or can be n-type doped using selected dopant elements. The layers and structures formed with both the ZnBeO and ZnCdSeO semiconductor alloys - including undoped, p-type-doped, and n-type-doped types - can be used for fabricating photonic and electronic semiconductor devices for use in photonic and electronic applications. These devices can be used in LEDs, LDs, FETs (field effect transistors), PN junctions, PIN junctions, Schottky barrier diodes, UV detectors and transmitters, and transistors and transparent transistors. They also can be used in applications for lightemitting display, backlighting for displays, UV and visible transmitters and detectors, high-frequency radar, biomedical imaging, chemical compound identification, molecular identification and structure, gas sensors, imaging systems, and for the fundamental studies of atoms, molecules, gases, vapors, and solids.

Ryu, Yungryel↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2009

Raman Channel Temperature Measurement of SiC MESFET as a Function of Ambient Temperature and DC Power

Raman spectroscopy is used to measure the junction temperature of a Cree SiC MESFET as a function of the ambient temperature and DC power. The carrier temperature, which is approximately equal to the ambient temperature, is varied from 25 C to 450 C, and the transistor is biased with VDS=10V and IDS of 50 mA and 100 mA. It is shown that the junction temperature is approximately 52 and 100 C higher than the ambient temperature for the DC power of 500 and 1000 mW, respectively.

Ponchak, George E.↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2009

Structure for implementation of back-illuminated CMOS or CCD imagers

A structure for implementation of back-illuminated CMOS or CCD imagers. An epitaxial silicon layer is connected with a passivation layer, acting as a junction anode. The epitaxial silicon layer converts light passing through the passivation layer and collected by the imaging structure to photoelectrons. A semiconductor well is also provided, located opposite the passivation layer with respect to the epitaxial silicon layer, acting as a junction cathode. Prior to detection, light does not pass through a dielectric separating interconnection metal layers.

Pain, Bedabrata↗
NASA NTRS2010

Self-Validating Thermocouple

Self-Validating Thermocouple (SVT) Systems capable of detecting sensor probe open circuits, short circuits, and unnoticeable faults such as a probe debonding and probe degradation are useful in the measurement of temperatures. SVT Systems provide such capabilities by incorporating a heating or excitation element into the measuring junction of the thermocouple. By heating the measuring junction and observing the decay time for the detected DC voltage signal, it is possible to indicate whether the thermocouple is bonded or debonded. A change in the thermal transfer function of the thermocouple system causes a change in the rise and decay times of the thermocouple output. Incorporation of the excitation element does not interfere with normal thermocouple operation, thus further allowing traditional validation procedures as well.

Perotti, Jose M.↗
NASA NTRS2011

Method for Providing Semiconductors Having Self-Aligned Ion Implant

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Neudeck, Philip G.↗
NASA NTRS2005

SCB Quantum Computers Using iSWAP and 1-Qubit Rotations

Units of superconducting circuitry that exploit the concept of the single- Cooper-pair box (SCB) have been built and are undergoing testing as prototypes of logic gates that could, in principle, constitute building blocks of clocked quantum computers. These units utilize quantized charge states as the quantum information-bearing degrees of freedom. An SCB is an artificial two-level quantum system that comprises a nanoscale superconducting electrode connected to a reservoir of Cooper-pair charges via a Josephson junction. The logical quantum states of the device, .0. and .1., are implemented physically as a pair of charge-number states that differ by 2e (where e is the charge of an electron). Typically, some 109 Cooper pairs are involved. Transitions between the logical states are accomplished by tunneling of Cooper pairs through the Josephson junction. Although the two-level system contains a macroscopic number of charges, in the superconducting regime, they behave collectively, as a Bose-Einstein condensate, making possible a coherent superposition of the two logical states. This possibility makes the SCB a candidate for the physical implementation of a qubit. A set of quantum logic operations and the gates that implement them is characterized as universal if, in principle, one can form combinations of the operations in the set to implement any desired quantum computation. To be able to design a practical quantum computer, one must first specify how to decompose any valid quantum computation into a sequence of elementary 1- and 2-qubit quantum gates that are universal and that can be realized in hardware that is feasible to fabricate. Traditionally, the set of universal gates has been taken to be the set of all 1-qubit quantum gates in conjunction with the controlled-NOT (CNOT) gate, which is a 2-qubit gate. Also, it has been known for some time that the SWAP gate, which implements square root of the simple 2-qubit exchange interaction, is as computationally universal as is the CNOT operation.

Williams, Colin↗
NASA NTRS2005

Making AlN(x) Tunnel Barriers Using a Low-Energy Nitrogen-Ion Beam

A technique based on accelerating positive nitrogen ions onto an aluminum layer has been demonstrated to be effective in forming thin (<2 nm thick) layers of aluminum nitride (AlN(x)) for use as tunnel barriers in Nb/Al-AlN(x)/Nb superconductor/insulator/ superconductor (SIS) Josephson junctions. AlN(x) is the present material of choice for tunnel barriers because, to a degree greater than that of any other suitable material, it offers the required combination of low leakage current at high current density and greater thermal stability. While ultra-thin AlN films with good thickness and stoichiometry control are easily formed using techniques such as reactive molecular beam epitaxy and chemical vapor deposition, growth temperatures of 900 C are necessary for the dissociative adsorption of nitrogen from either nitrogen (N2) or ammonia (NH3). These growth temperatures are prohibitively high for the formation of tunnel barriers on Nb films because interfacial reactions at temperatures as low as 200 to 300 C degrade device properties. Heretofore, deposition by reactive sputtering and nitridation of thin Al layers with DC and RF nitrogen plasmas have been successfully used to form AlN barriers in SIS junctions. However, precise control over critical current density Jc has proven to be a challenge, as is attaining adequate process reproducibility from system to system. The present ion-beam technique is an alternative to the plasma or reactive sputtering techniques as it provides a highly controlled arrival of reactive species, independent of the electrical conditions of the substrate or vacuum chamber. Independent and accurate control of parameters such as ion energy, flux, species, and direction promises more precise control of film characteristics such as stoichiometry and thickness than is the case with typical plasma processes. In particular, the background pressure during ion-beam nitride growth is 2 or 3 orders of magnitude lower, minimizing the formation of compounds with contaminants, which is critical in devices the performance of which is dictated by interfacial characteristics. In addition, the flux of incoming species can be measured in situ using ion probes so that the dose can be controlled accurately. The apparatus used in the present ion-beam technique includes a vacuum chamber containing a commercial collimated- ion-beam source, a supply of nitrogen and argon, and an ion probe for measuring the ion dose. Either argon or nitrogen can be used as the feed gases for the ion source, depending on whether cleaning of the substrate or growth of the nitride, respectively, is desired. Once the Nb base electrode and Al proximity layer have been deposited, the N2 gas line to the ion beam is vented and purged, and the ion-source is turned on until a stable discharge is obtained. The substrate is moved over the ion-beam source to expose the Al surface layer to the ion beam (see figure) for a specified duration for the formation of the nitride tunnel barrier. Next, the Nb counter-electrode layer is deposited on the nitride surface layer. The Nb/Al- AlN(x)/Nb-trilayer-covered substrate is then patterned into individual devices by use of conventional integrated-circuit processing techniques.

Kaul, Anupama↗