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At least 1,639 records · Page 91

All sources NASA NTRS DOE OSTI

DOE OSTI2014

Optical systems fabricated by printing-based assembly

Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.

47 OTHER INSTRUMENTATION↗

DOE OSTI2014

Rigid spine reinforced polymer microelectrode array probe and method of fabrication

A rigid spine-reinforced microelectrode array probe and fabrication method. The probe includes a flexible elongated probe body with conductive lines enclosed within a polymeric material. The conductive lines connect microelectrodes found near an insertion end of the probe to respective leads at a connector end of the probe. The probe also includes a rigid spine, such as made from titanium, fixedly attached to the probe body to structurally reinforce the probe body and enable the typically flexible probe body to penetrate and be inserted into tissue, such as neural tissue. By attaching or otherwise fabricating the rigid spine to connect to only an insertion section of the probe body, an integrally connected cable section of the probe body may remain flexible.

47 OTHER INSTRUMENTATION↗

DOE OSTI2014

Contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication

Methods for contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication are provided. In one embodiment, a method for fabricating an electrical semiconductor device comprises: a first step that includes gettering of impurities from a semiconductor wafer and forming a backsurface field; and a second step that includes forming a front contact for the semiconductor wafer, wherein the second step is performed after completion of the first step.

36 MATERIALS SCIENCE↗

DOE OSTI2014

Method of fabricating a back-contact solar cell and device thereof

Methods of fabricating back-contact solar cells and devices thereof are described. A method of fabricating a back-contact solar cell includes forming an N-type dopant source layer and a P-type dopant source layer above a material layer disposed above a substrate. The N-type dopant source layer is spaced apart from the P-type dopant source layer. The N-type dopant source layer and the P-type dopant source layer are heated. Subsequently, a trench is formed in the material layer, between the N-type and P-type dopant source layers.

36 MATERIALS SCIENCE↗

DOE OSTI2014

Semiconductor device PN junction fabrication using optical processing of amorphous semiconductor material

Systems and methods for semiconductor device PN junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a P-N junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material.

14 SOLAR ENERGY↗

DOE OSTI2014

Method of fabricating vertically aligned group III-V nanowires

A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.

36 MATERIALS SCIENCE↗

DOE OSTI2015

Vertical group III-V nanowires on si, heterostructures, flexible arrays and fabrication

Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures. An array of Group III-V nanowire structures is embedded in polymer. A fabrication method forms the vertical nanowires on a substrate, e.g., a silicon substrate. Preferably, the nanowires are formed by the preferred methods for fabrication of Group III-V nanowires on silicon. Devices can be formed with core/shell and core/multi-shell nanowires and the devices are released from the substrate upon which the nanowires were formed to create a flexible structure that includes an array of vertical nanowires embedded in polymer.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

DOE OSTI2015

Design Fabrication and Characterization of High Density Silicon Photonic Components

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve e ciency while reducing on-chip area even as photonic components expand to ll application spaces no longer satis ed by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which e cient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling on a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the rst experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modi ed racetrack resonator is then presented enabling extraction of insertion loss data for highly e cient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.

36 MATERIALS SCIENCE↗

DOE OSTI2015

Dopant ink composition and method of fabricating a solar cell there from

Dopant ink compositions and methods of fabricating solar cells there from are described. A dopant ink composition may include a cross-linkable matrix precursor, a bound dopant species, and a solvent. A method of fabricating a solar cell may include delivering a dopant ink composition to a region above a substrate. The dopant ink composition includes a cross-linkable matrix precursor, a bound dopant species, and a solvent. The method also includes baking the dopant ink composition to remove a substantial portion of the solvent of the dopant ink composition, curing the baked dopant ink composition to cross-link a substantial portion of the cross-linkable matrix precursor of the dopant ink composition, and driving dopants from the cured dopant ink composition toward the substrate.

14 SOLAR ENERGY↗

DOE OSTI2015

Mixed ionic-electronic conductor-based radiation detectors and methods of fabrication

A method of fabricating a mixed ionic-electronic conductor (e.g. TlBr)-based radiation detector having halide-treated surfaces and associated methods of fabrication, which controls polarization of the mixed ionic-electronic MIEC material to improve stability and operational lifetime.

36 MATERIALS SCIENCE↗

DOE OSTI2015

Optical systems fabricated by printing-based assembly

47 OTHER INSTRUMENTATION↗

DOE OSTI2015

Fabrication of small-scale structures with non-planar features

The fabrication of small-scale structures is disclosed. A unit-cell of a small-scale structure with non-planar features is fabricated by forming a membrane on a suitable material. A pattern is formed in the membrane and a portion of the substrate underneath the membrane is removed to form a cavity. Resonators are then directionally deposited on the wall or sides of the cavity. The cavity may be rotated during deposition to form closed-loop resonators. The resonators may be non-planar. The unit-cells can be formed in a layer that includes an array of unit-cells.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2015

Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

36 MATERIALS SCIENCE↗

DOE OSTI2015

Method of fabrication of supported liquid membranes

Method for the fabrication of a supported liquid membrane having a dense layer in contact with a porous layer, and a membrane liquid layer within the interconnected pores of the porous layer. The dense layer is comprised of a solidified material having an average pore size less than or equal to about 0.1 nanometer, while the porous layer is comprised of a plurality of interconnected pores and has an average pore size greater than 10 nanometers. The supported liquid membrane is fabricated through the preparation of a casting solution of a membrane liquid and a volatile solvent. A pressure difference is established across the dense layer and porous layer, the casting solution is applied to the porous layer, and the low viscosity casting solution is drawn toward the dense layer. The volatile solvent is evaporated and the membrane liquid precipitates, generating a membrane liquid layer in close proximity to the dense layer.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

DOE OSTI2016

Method of fabricating a back-contact solar cell and device thereof

14 SOLAR ENERGY↗

DOE OSTI2016

Neutron detector and fabrication method thereof

A neutron detector and a method for fabricating a neutron detector. The neutron detector includes a photodetector, and a solid-state scintillator operatively coupled to the photodetector. In one aspect, the method for fabricating a neutron detector includes providing a photodetector, and depositing a solid-state scintillator on the photodetector to form a detector structure.

36 MATERIALS SCIENCE↗

DOE OSTI2015

LBNF 1.2 MW TARGET: CONCEPTUAL DESIGN & FABRICATION

Fermilab’s Long-Baseline Neutrino Facility (LBNF) will utilize a modified design based on the NuMI low energy target that is reconfigured to accommodate beam operation at 1.2 MW. Achieving this power with a graphite target material and ancillary systems originally rated for 400 kW requires several design changes and R&D efforts related to material bonding and electrical isolation. Target cooling, structural design, and fabrication techniques must address higher stresses and heat loads that will be present during 1.2 MW operation, as the assembly will be subject to cyclic loads and thermal expansion. Mitigations must be balanced against compromises in neutrino yield. Beam monitoring and subsystem instrumentation will be updated and added to ensure confidence in target positioning and monitoring. Remote connection to the target hall support structure must provide for the eventual upgrade to a 2.4 MW target design, without producing excessive radioactive waste or unreasonable exposure to technicians during reconfiguration. Current designs and assembly layouts will be presented, in addition to current findings on processes and possibilities for prototype and final assembly fabrication.

43 PARTICLE ACCELERATORS↗

DOE OSTI2014

OpenSoC Fabric

Recent advancements in technology scaling have shown a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation proves insufficient to study the tradeoffs in such complex systems due to slow execution time, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, an on-chip network generation infrastructure which aims to provide a parameterizable and powerful on-chip network generator for evaluating future high performance computing architectures based on SoC technology. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. The OpenSoC Fabric2 infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and follows object-oriented design and functional programming to make functionality extension as easy as possible.

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