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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Interfacial oxide and other species in trimethylaluminum-pretreated atomic layer deposition-Al 2 O 3 /GaN characterized by sputter-assisted ToF-SIMS

Deposition techniques, like atomic layer deposition (ALD), are used to form high-quality dielectrics for GaN-based metal–oxide–semiconductor (MOS) gate structures due to the lack of a reliable thermal oxide in GaN. Moreover, interfacial GaO x from pre-existing native oxides is thought to adversely impact channel carrier dynamics and induce undesired threshold voltage shifts in GaN-based MOS gate structures. Exposure of the GaN surface to the trimethylaluminum (TMA) precursor prior to standard alumina ALD decreases the native oxide layer on GaN, but the extent of chemical modification has not been well studied in the context of interface composition in a MOS gate structure. Herein, we compare annealed 55 nm Al 2 O 3 dielectric films on GaN grown using either a water-first ALD process or a process including sequential pulses of TMA immediately before the initiation of Al 2 O 3 ALD. Time-of-Flight Secondary Ion Mass Spectrometry measures differences in the interfacial GaO x content between each ALD film. Here, it also detects surface contaminant species like Si, F, S, and C. Furthermore, we report the formation of an AlN species at the Al 2 O 3 /GaN interface, which is more prominent for the film grown using the TMA pre-pulse step. In general, this work demonstrates that the TMA pre-pulse step is an effective strategy for cleaning substrate surfaces prior to ALD.

Atomic layer deposition↗
DOE OSTI2025

On Rate-Limiting Mechanisms in NMC Cathodes: The Interplay of Low and High Current Constraints

In this study, we investigate the rate performance limits in LiNi 0.6 Mn 0.2 Co 0.2 O 2 cathodes for lithium-ion batteries, focusing on how cathode thickness, porosity, and threshold voltage impact discharge capacity. By conducting galvanostatic discharge experiments across a wide range of current densities using cathodes of varying thicknesses and porosities, we identify two distinct rate-limiting mechanisms: ionic liquid-diffusion and Ohmic/charge-transfer limitations. Our findings show that thick, dense cathodes are primarily limited by lithium diffusion in the electrolyte, while thinner and more porous cathodes are dominated by Ohmic/charge-transfer limitations, particularly at higher lower cutoff voltages. Crucially, these results allow us to identify the rate-limiting mechanisms in different cathode configurations, offering clear insights into how cathode design can be optimized for improved performance. Understanding these mechanisms is essential for designing next-generation batteries with enhanced rate performance, which is critical for applications such as electric vehicles and renewable energy storage systems.

Brischetto, Martin (ORCID:0000000339865813)↗
DOE OSTI2024

Electron Density Measurements Using USPR (Final Scientific/Technical Report)

UC Davis has fabricated an ultrashort pulse reflectometer (USPR) diagnostic instrument for electron density profile measurements on compact, short duration, magnetically-confined fusion-energy concept devices such as spheromaks and FRCs. The USPR system transmits extremely short duration (~few nsec) chirped waveforms that together span 29 to 75 GHz. These chirped waveforms illuminate and reflect from the target plasma, with each frequency component reflecting from a different density layer (higher frequencies probe deeper into the plasma before reflecting). The reflected waveforms are split into roughly 42 different frequencies; time-of-flight (TOF) measurements made at each frequency with high resolution (~25 psec measurement resolution which corresponds to ~5 mm). These TOF data may then be inverted via software to generate electron density profiles with high time resolution (~10 μsec). At the heart of the system is a field programmable gate array (FPGA) based controller which collects and processes all of the USPR data in addition to generating all of the control signals required for maximum flexibility. The FPGA controller has the software flexibility to be easily reconfigured for different plasma devices, and the entire system sufficiently compact to be easily and quickly transported between devices. A high speed impulse generator was transformed into a set of three ultrashort pulse transmitter chirps using a combination of dispersive waveguide, frequency doublers and high-pass filters. A mm-wave controller was fabricated to sequentially switch between the three chirps, directing the chirps one-by-one to three different mm-wave assemblies spanning 29-75 GHz. Each mm-wave assembly consists of a high power active multiplier chain which converts the transmitter chirp to higher frequencies, and a broadband mixer which downconverts the reflected waveform to the 2-18 GHz range of the UPSR receiver. The 16-channel receiver (shared by all 3 mm-wave assemblies) was fabricated employing custom TOF modules capable of operating at a high 1 MHz sampling rate. Laboratory testing of the full system revealed the presence of unwanted harmonics from the multiplication process, with interference observed in the downconverted reflections at selected frequency channels that could not be completely filtered out. Additional interference effects arising from internal reflections within the mm-wave assemblies were minimized using a high-speed switch which served to “gate out” much of these reflections. The USPR diagnostic was transported and installed onto the HIT-SIU plasma device, becoming operational on 11/08/2022. Although designed to span 3 distinct mm-wave bands, the HIT-SIU plasmas at this time were sufficiently low density such that only the lowest of the three bands was likely to have strong plasma reflections. The system was then set to operate on only the lowest band (assembly #1), with data collected every 1 μsec rather than 3 μsec which would have been the case when cycling through all three bands. Connected to HIT-SIU, time-varying plasma reflections were observed on 9 of 16 possible frequency channels. Close examination of the data collected revealed issues previously unobserved in laboratory testing, associated with (a) reflections from the small aperture horns required for operation within the HIT-SIU device, and (b) a dependence of the recorded TOF with the threshold voltage of a given channel. Plans were made to address each of these issues before undertaking any future campaigns.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

CMS HGCAL ECON-D ASIC : Impact of CMOS fabrication process tuning on performance and radiation tolerance

The CMS experiment’s High Granularity Calorimeter (HGCAL) upgrade will replace CMS’s existing endcap calorimeters in preparation for the High Luminosity LHC. To effectively use over 6 million channels of this “imaging”calorimeter, CMS has developed two novel Endcap Concentrator (ECON) ASICs to perform data compression/selection on detector. The ECON-D ASIC operates on the 750kHz data path, and the ECON-T ASIC on the 40MHz trigger path. These 65 nm CMOS ASICs are radiation tolerant to 200 Mrad and low power, operating at less than 2.5 mW/channel. The first full-functionality prototype ECONs were produced and characterized in 2021-23, and an initial engineering run was performed in 2024. ECON-D radiation testing for the engineering run revealed that the chip’s internal SRAMs produce intermittent read errors for a non-negligible fraction of chips. Further investigation indicated that the SRAM performance is highly sensitive to the exact parameters of the CMOS fabrication process. To both study this process sensitivity and mitigate SRAM performance issues, twenty ECON wafers were produced in 2025 with a range of doping concentrations designed to tune the underlying transistor threshold voltage by 0%, 5%, 10%, and 15% from nominal. This talk will present first measurements of ECON-D performance, power consumption, and radiation tolerance for these four variations of CMOS process.

Syal, Chinar [Fermilab]↗
DOE OSTI2026

Learned adaptive properties for mitigation of weight perturbations in embedded spiking networks

Recent years have seen an increased importance of neural network inference in edge-based scenarios, which impose size and power constraints requiring novel computing devices. These same edge scenarios may require operating over long periods of time, or exposure to extreme environments, resulting in a drift of neural network weights that cause degraded performance. In searching for ways to develop neural network approaches that perform robustly under these conditions, we propose a biologically-inspired mechanism for the dynamic adaptation of within-neuron parameters that is guided by a global context signal carrying information about perturbations and variability in incoming stimuli. Specifically, we demonstrate that adaptive voltage thresholds or neuronal time constants, when informed by a global context signal, can enable network-level mechanisms to recover from perturbed synaptic weights. Consistent with prior literature, the context-modulated approach is effective for recurrent, but not feedforward networks, by modulating network level dynamics. We demonstrate this approach successfully recovers performance in image classification tasks and spatiotemporal tracking tasks under idealized and Gaussian noise as well as for realistic perturbations from a memristive device when exposed to ionizing radiation. Finally, we discuss how this approach enables the design of robust and energy-efficient neuromorphic systems that perform well, even in resource-constrained scenarios with extreme environments such as edge processing.

context modulation↗
DOE OSTI2023

AlGaN High Electron Mobility Transistor for High-Temperature Logic

Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

42 ENGINEERING↗
NASA NTRS1967

Low cost SCR lamp driver indicates contents of digital computer registers

Silicon Controlled Rectifier /SCR/ lamp driver is adapted for use in integrated circuit digital computers where it indicates the contents of the various registers. The threshold voltage at which visual indication begins is very sharply defined and can be adjusted to suit particular system requirements.

Cliff, R. A.↗
NASA NTRS1971

Electrical properties of tellurium thin films

Evaporated tellurium thin films electric properties, discussing fabrication techniques, temperature dependence, field effect and Hall mobilities, threshold voltage and stability

Dutton, R. W.↗
NASA NTRS1975

Effects of ionizing radiation on CCD's

The effects of 1.2 MeV gamma radiation and 20 MeV electrons on the operational characteristics of CCDs are studied. The effects of ionizing radiation on the charge transfer efficiency, dark current, and input/output circuitry are described. The improved radiation hardness of buried channel CCDs is compared to surface channel results. Both ion implanted and epitaxial layer buried channel device results are included. The advantages of using a single thickness SiO2 gate dielectric are described. The threshold voltage shifts and surface state density changes of dry, steam, and HCl doped oxides are discussed. Recent results on the recovery times and total dose effects of high dose rate pulses of 20 MeV electrons are reported.

Hartsell, G. A.↗
NASA NTRS1975

Effects of radiation on charge-coupled devices

The effects of 1 MeV electron irradiation upon the performance of two phase, polysilicon aluminum gate CCDs are reported. Both n- and p-surface channel and n-buried channel devices are investigated using 64- and 128-stage line arrays. Characteristics measured as a function of radiation dose include: Transfer inefficiency, threshold voltage, field effect mobility, interface state density, full well signal level and dark current. Surface channel devices are found to degrade considerably at less than 10 to the 5th power rads (Si) due to the large increase in fast interface state density caused by radiation. Buried channel devices maintain efficient operation to the highest dose levels used.

Carnes, J. E.↗
NASA NTRS1976

Shuttle spectrum despreader

The results of the spread spectrum despreader project are reported and three principal products are designed and tested. The products are, (1) a spread spectrum despreader breadboard, (2) associated test equipment consisting of a spectrum spreader and bit reconstruction/error counter and (3) paper design of a Ku-band receiver which would incorporate the despreader as a principal subsystem. The despreader and test set are designed for maximum flexibility. A choice of unbalanced quadriphase or biphase shift keyed data modulation is available. Selectable integration time and threshold voltages on the despreader further lend true usefulness as laboratory test equipment to the delivered hardware.

Source record↗
NASA NTRS1975

Tunnel injection into gate oxide traps

An experimental method is described for measuring the density of oxide traps in the gate oxide of an MOS transistor as a function of energy and position near the silicon interface. Measurements are obtained from different oxide growth processes and after Co-60 irradiation. The results are related to long-term drift of threshold voltage.

Maserjian, J.↗