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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

Onboard Autonomous Trajectory Planning for Mars Power Descent

In recent years, there has been an increasing interest in space-qualified processors such as multi-core central processing units and graphics processing units that can withstand the adverse effects of space radiation. These processors can allow parallel programming to perform tasks that typically demand high computational power. One can study guidance schemes that can take advantage of these currently developing processors and provide more robust guidance. Software for Multi-model Autonomous Real-time Trajectories (SMART) guidance can identify robust trajectories by running an onboard Monte Carlo analysis. SMART guidance can take advantage of knowledge updates obtained from the onboard sensors, allowing it to consider the off-nominal cases that it would not typically encounter during the offline trajectory analysis. This work uses the SMART guidance for the powered divert at Mars simulation in Program to Optimize and Simulated Trajectories- II.

Autonomous Planning↗
NASA NTRS2001

Automation of Data Traffic Control on DSM Architecture

The design of distributed shared memory (DSM) computers liberates users from the duty to distribute data across processors and allows for the incremental development of parallel programs using, for example, OpenMP or Java threads. DSM architecture greatly simplifies the development of parallel programs having good performance on a few processors. However, to achieve a good program scalability on DSM computers requires that the user understand data flow in the application and use various techniques to avoid data traffic congestions. In this paper we discuss a number of such techniques, including data blocking, data placement, data transposition and page size control and evaluate their efficiency on the NAS (NASA Advanced Supercomputing) Parallel Benchmarks. We also present a tool which automates the detection of constructs causing data congestions in Fortran array oriented codes and advises the user on code transformations for improving data traffic in the application.

Frumkin, Michael↗
NASA NTRS1996

Research of TREETOPS Structural Dynamics Controls Simulation Upgrade

Under the provisions of contract number NAS8-40194, which was entitled 'TREETOPS Structural Dynamics and Controls Simulation System Upgrade', Oakwood College contracted to produce an upgrade to the existing TREETOPS suite of analysis tools. This suite includes the main simulation program, TREETOPS, two interactive preprocessors, TREESET and TREEFLX, an interactive post processor, TREEPLOT, and an adjunct program, TREESEL. A 'Software Design Document', which provides descriptions of the argument lists and internal variables for each subroutine in the TREETOPS suite, was established. Additionally, installation guides for both DOS and UNIX platforms were developed. Finally, updated User's Manuals, as well as a Theory Manual, were generated.

Yates, Rose M.↗
NASA NTRS1999

Initial Flight Test of the Production Support Flight Control Computers at NASA Dryden Flight Research Center

The NASA Dryden Flight Research Center has completed the initial flight test of a modified set of F/A-18 flight control computers that gives the aircraft a research control law capability. The production support flight control computers (PSFCC) provide an increased capability for flight research in the control law, handling qualities, and flight systems areas. The PSFCC feature a research flight control processor that is "piggybacked" onto the baseline F/A-18 flight control system. This research processor allows for pilot selection of research control law operation in flight. To validate flight operation, a replication of a standard F/A-18 control law was programmed into the research processor and flight-tested over a limited envelope. This paper provides a brief description of the system, summarizes the initial flight test of the PSFCC, and describes future experiments for the PSFCC.

Carter, John↗
NASA NTRS1992

Initializing Embedded Data Processors From A Single Source

Initial-computer-program-loading system provides startup information to all embedded data processors (EDP's) in general-purpose computer system. Remote processors given image of startup diskette so real local diskette and drive unneeded. System less complex and equipment costs less. Additional benefit, initial program loading tests bus. If boot-up program transmitted correctly, bus assumed to be operating properly.

Chavez, Edward A.↗
NASA NTRS1973

A series-resonant silicon-controlled-rectifier power processor for ion thrusters

A program to develop a power processing system for ion thrusters is presented. Basic operation of the silicon controlled rectifier series inverter circuitry is examined. The approach for synthesizing such circuits into a system which limits the electrical stress levels on the power source, semiconductor switching elements, and the ion thruster load is described. Experimental results are presented for a 2.5-kW breadboard system designed to operate a 20-cm ion thruster.

Shumaker, H. A.↗
NASA NTRS1981

Command system output bit verification

An automatic test was developed to test the ability of the deep space station (DSS) command subsystem and exciter to generate and radiate, from the exciter, the correct idle bit sequence for a given flight project or to store and radiate received command data elements and files without alteration. This test, called the command system output bit verification test, is an extension of the command system performance test (SPT) and can be selected as an SPT option. The test compares the bit stream radiated from the DSS exciter with reference sequences generated by the SPT software program. The command subsystem and exciter are verified when the bit stream and reference sequences are identical. It is a key element of the acceptance testing conducted on the command processor assembly (CPA) operational program (DMC-0584-OP-G) prior to its transfer from development to operations.

Odd, C. W.↗
NASA NTRS1978

SPAR data handling utilities

The SPAR computer software system is a collection of processors that perform particular steps in the finite-element structural analysis procedure. The data generated by each processor are stored on a data base complex residing on an auxiliary storage device, and these data are then used by subsequent processors. The SPAR data handling utilities use routines to transfer data between the processors and the data base complex. A detailed description of the data base complex organization is presented. A discussion of how these SPAR data handling utilities are used in an application program to perform desired user functions is given with the steps necessary to convert an existing program to a SPAR processor by incorporating these utilities. Finally, a sample SPAR processor is included to illustrate the use of the data handling utilities.

Giles, G. L.↗
NASA NTRS1986

Distributed Ada: Methodology, notation and tools

The task of creating software to run on a distributed system brings with it many problems not encountered in a uni-processor environment. The designer, in addition to creating a solution to meet the functional requirements of the applicaiton, must determine how to distribute that functionality in order to meet the nonfunctional requirements such as performance and fault tolerance. In the traditional approach to building distributed software systems, decisions of how to partition the software must be made early in the design process so that a separate program can be written for each of the processors in the system. This design paradigm is extremely vulnerable to changes in the target hardware environment, as well as being sensitive to poor initial guesses about what distribution of functionality will satisfy the nonfunctional requirements. The paradigm is also weak in that no compiler has a complete view of the system. Many of the advantages of using a powerful language system are lost in a one-program-per-processor environment. Another approach to the development of distributed software systems, Honeywell's Distributed Ada program, is presented.

Eisenhauer, Greg↗
NASA NTRS2016

Selection of a Brine Processor Technology for NASA Manned Missions

The current ISS Water Recovery System (WRS) reclaims water from crew urine, humidity condensate, and Sabatier product water. Urine is initially processed by the Urine Processor Assembly (UPA) which recovers 75% of the urine as distillate. The remainder of the water is present in the waste brine which is currently disposed of as trash on ISS. For future missions this additional water must be reclaimed due to the significant resupply penalty for missions beyond Low Earth Orbit (LEO). NASA has pursued various technology development programs for a brine processor in the past several years. This effort has culminated in a technology down-select to identify the optimum technology for future manned missions. The technology selection is based on various criteria, including mass, power, reliability, maintainability, and safety. Beginning in 2016 the selected technology will be transitioned to a flight hardware program for demonstration on ISS. This paper summarizes the technology selection process, the competing technologies, and the rationale for the technology selected for future manned missions.

Carter, Donald L.↗
NASA NTRS1988

Explicit and implicit solution of the Navier-Stokes equations on a massively parallel computer

The design, implementation, and performance of a two-dimensional time-accurate Navier-Stokes solver for the CM2 supercomputer are described. The program uses a single processor for each grid point. Two different time-stepping methods have so far been implemented: an explicit third-order Runge-Kutta method and an implicit approximation-factorization method. The CM2 results are checked against those of a mature well-vectorized Cray 2 program, both for correctness and performance. The code is found to be correct, and the performance in some cases is up to several times that of the Cray 2.

Levit, Creon↗
NASA NTRS1975

A reliability tradeoff study of interconnecting power processors to mercury ion thrusters

A Monte Carlo mission simulation program has been developed to optimize the solar electric propulsion (SEP) thrust subsystem configuration for an Encke comet rendezvous mission. This program examines several possible options for interconnecting power processors to the mercury ion thrusters in order to enhance mission reliability and to reduce SEP subsystem weight. The quantity of power processors and ion thrusters required to perform the mission successfully depends not only on the total required thrust, but also on the individual thruster and power processor performance and reliability. Based on these considerations, it was necessary to determine the quantity of the active power processors and ion thrusters required at any time and the means of providing redundancy. The results provide the basis for selecting an optimum SEP thrust subsystem for this mission and other missions.

Costogue, E. N.↗
NASA NTRS1992

Fault detection and bypass in a sequence information signal processor

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

Peterson, John C.↗
NASA NTRS1979

Detailed description of the HP-9825A HFRMP trajectory processor (TRAJ)

The computer code for the trajectory processor of the HP-9825A High Fidelity Relative Motion Program is described in detail. The processor is a 12-degrees-of-freedom trajectory integrator which can be used to generate digital and graphical data describing the relative motion of the Space Shuttle Orbiter and a free-flying cylindrical payload. Coding standards and flow charts are given and the computational logic is discussed.

Kindall, S. M.↗
NASA NTRS1985

A VHSIC general purpose processor

The very high speed integrated circuit (VHSIC) program offers NASA and its contractors assured availability of military specification embedded computer components and integrated computer aided design/computer aided engineering and software development support that result in low system life costs for data management systems on the space station and the Earth Observatory Satellite. Viewgraphs given review progress in both the Department of Defense VHSIC program and the NASA VHSIC related insertion development of a general purpose processor are presented.

Benz, H. F.↗