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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Systems and methods for shock-resistant memory devices

A shock-resistant memory device comprises a housing and a memory module. The memory module is disposed within the housing and surrounded by potting material to protect the memory module from damage during a shock event. The housing can include a port that accommodates a data connection between the memory module and a sensor from which data is desirably received by the memory module. During a shock event the connection between the memory module and the sensor may be severed, but data stored in the memory module can be retained in the memory module which is protected by the housing. To facilitate retrieval of the memory device subsequent to a shock event, a balloon can be affixed to the housing. The balloon can be configured to inflate subsequent to the shock event so that the shock-resistant memory device does not sink in water and to make the memory device more visible for recovery.

42 ENGINEERING↗
DOE OSTI2021

Rats use memory confidence to guide decisions

Memory enables access to past experiences to guide future behavior. Humans can determine which memories to trust (high confidence) and which to doubt (low confidence). How memory retrieval, memory confidence, and memory-guided decisions are related, however, is not understood. In particular, how confidence in memories is used in decision making is unknown. We developed a spatial memory task in which rats were incentivized to gamble their time: betting more following a correct choice yielded greater reward. Rat behavior reflected memory confidence, with higher temporal bets following correct choices. We applied machine learning to identify a memory decision variable and built a generative model of memories evolving over time that accurately predicted both choices and confidence reports. Our results reveal in rats an ability thought to exist exclusively in primates and introduce a unified model of memory dynamics, retrieval, choice, and confidence.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2017

Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” and if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Memory forensic analysis of a programmable logic controller in industrial control systems

In industrial control systems (ICS), programmable logic controllers (PLCs) are used to automate physical processes such as nuclear plants and power grid stations, and are often subject to cyber attacks. As in conventional IT domain, the memory analysis of the PLCs can help answer important forensic questions about the attack, such as the presence of malicious firmware, injection of modified control logic (the program running on the PLC), and manipulation of I/O devices (e.g., sensors and actuators). Unlike conventional IT domain, PLCs have heterogeneous hardware architecture, proprietary firmware and control software, making it challenging to employ a unified framework for their memory forensics. For merely extracting artifacts of forensic importance, reverse-engineering the firmware is a tedious task, and the effort needs to be repeated for every PLC model. As a community, a step-wise approach to tackle this challenge is to analyze the memory of specific PLCs, and subsequently find a generic framework applicable to all PLCs. Our work is a step forward in this direction. By following a methodology that focuses on the functional layer of PLCs instead of reverse engineering the firmware, we analyze the digital forensic artifacts available in a common PLC, Allen-Bradley ControlLogix 1756-L61. Before diving into the memory dump, we analyze the PLC control software to create a list of important artifacts that are sure to exist in the PLC memory dump. The approach employs a setup where PLC control software RSLogix-5000 is connected to the PLC, and the memory dump can be obtained as and when needed. We create test cases that sequentially highlight each category of artifacts, followed by an examination of the resultant impact on memory. After attaining the listed artifacts, we employ conventional string and known data searches to extract interesting information present in this PLC's memory. The memory analysis profile, presented as a Python library and shared with the community, can help a forensic investigator to readily extract forensic artifacts from the same model's controller. The adopted approach may help researchers in creating memory profile of other PLCs, and ultimately formulating a generic PLC memory analysis framework.

Rais, Muhammad Haris↗
DOE OSTI2023

A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths

The dream of achieving a universal memory that can provide robust non-volatile memory states along with low-energy operation has been the key driving force of memory research. Despite dominating the memory market, conventional charge-based memories cannot satisfy these requirements. However, UltraRAM, an oxide-free charge-based memory cell, aims to achieve both of these requirements. This device achieves non-volatility (with an endurance of over 10 7 cycles and a retention of over 1000 years) along with switching at low-voltage (±2.3 V) utilizing a triple-barrier resonant tunneling (TBRT) structure made of InAs/AlSb. In this work, we propose an array design for UltraRAM-based memory devices. Our proposed memory array features separate read-write path and eliminates the possibility of accidentally switching the memory states stored in the array. Moreover, our design allows us to read all the cells in a column in one cycle without imposing any limit on the scalability. Besides, since the read operation in our proposed design is independent of the write mechanism, there is flexibility to optimize the read operation for memory and in-memory computing applications.

Alam, Shamiul↗
DOE OSTI2019

Machine learning based design space exploration for hybrid main-memory design

We develop a machine learning (ML) based design space exploration (DSE) method that builds predictive models for various responses of a hybrid main-memory system. To overcome the challenges associated with latency, capacity, and power of memory systems in future extreme-scale machines, the hybrid memory architectures are being considered in which novel non-volatile memory (NVM) systems augment the traditional DRAM. However, way before their actual design and implementation, these emerging hybrid memory systems need to be simulated and analyzed to fully understand their capabilities and limitations. As the conventional architectural-level memory simulators require significant amounts of computational costs and time, we propose to utilize ML techniques for developing various memory-response models that can instantly provide a predicted response corresponding to any new memory configuration. Specifically, in this work, we apply four supervised ML techniques to build regression models for memory latency, bandwidth, power, and total read/write responses. The training and validation data for the ML methods are generated using NVMain memory simulator for DRAM, NVM, and their hybrid combinations. We demonstrate the results of the ML based memory-DSE method in terms of the learning curve characteristics for hyperparameter tuning and the statistical error analyses of the designed predictive models.

Sen, Satyabrata↗
DOE OSTI2016

Strategic priming with multiple antigens can yield memory cell phenotypes optimized for infection with Mycobacterium tuberculosis : A computational study

Lack of an effective vaccine results in 9 million new cases of tuberculosis (TB) every year and 1.8 million deaths worldwide. While many infants are vaccinated at birth with BCG (an attenuated M. bovis ), this does not prevent infection or development of TB after childhood. Immune responses necessary for prevention of infection or disease are still unknown, making development of effective vaccines against TB challenging. Several new vaccines are ready for human clinical trials, but these trials are difficult and expensive; especially challenging is determining the appropriate cellular response necessary for protection. The magnitude of an immune response is likely key to generating a successful vaccine. Characteristics such as numbers of central memory (CM) and effector memory (EM) T cells responsive to a diverse set of epitopes are also correlated with protection. Promising vaccines against TB contain mycobacterial subunit antigens (Ag) present during both active and latent infection. We hypothesize that protection against different key immunodominant antigens could require a vaccine that produces different levels of EM and CM for each Ag-specific memory population. We created a computational model to explore EM and CM values, and their ratio, within what we term Memory Design Space. Our model captures events involved in T cell priming within lymph nodes and tracks their circulation through blood to peripheral tissues. We used the model to test whether multiple Ag-specific memory cell populations could be generated with distinct locations within Memory Design Space at a specific time point post vaccination. Boosting can further shift memory populations to memory cell ratios unreachable by initial priming events. By strategically varying antigen load, properties of cellular interactions within the LN, and delivery parameters (e.g., number of boosts) of multi-subunit vaccines, we can generate multiple Ag-specific memory populations that cover a wide range of Memory Design Space. As a result, given a set of desired characteristics for Ag-specific memory populations, we can use our model as a tool to predict vaccine formulations that will generate those populations.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

DeepPhenoMem V1.0: deep learning modelling of canopy greenness dynamics accounting for multi-variate meteorological memory effects on vegetation phenology

Abstract. Vegetation phenology plays a key role in controlling the seasonality of ecosystem processes that modulate carbon, water and energy fluxes between the biosphere and atmosphere. Accurate modelling of vegetation phenology in the interplay of Earth's surface and the atmosphere is thus crucial to understand how the coupled system will respond to and shape climatic changes. Phenology is controlled by meteorological conditions at different timescales: on the one hand, changes in key meteorological variables (temperature, water, radiation) can have immediate effects on the vegetation development; on the other hand, phenological changes can be driven by past environmental conditions, known as memory effects. However, the processes governing meteorological memory effects on phenology are not completely understood, resulting in their limited performance of vegetation phenology represented in land surface models. A deep learning model, specifically a long short-term memory network (LSTM), has the potential to capture and model the meteorological memory effects on vegetation phenology. Here, we apply the LSTM to model the vegetation phenology using meteorological drivers and high-temporal-resolution canopy greenness observations through digital repeat photography by the PhenoCam network. We compare a multiple linear regression model, a no-memory-effect LSTM model and a full-memory-effect LSTM model to predict the whole seasonal greenness trajectory and the corresponding phenological transition dates across 50 sites and 317 site years during 2009–2018, covering deciduous broadleaf forests, evergreen needleleaf forests and grasslands. Results show that the deep learning model outperforms the multiple linear regression model, and the full-memory-effect LSTM model performs better than the no-memory-effect model for all three plant function types (median R2 of 0.878, 0.957 and 0.955 for broadleaf forests, evergreen needleleaf forests and grasslands). We also find that the full-memory-effect LSTM model is capable of predicting the seasonal dynamic variations of canopy greenness and reproducing trends in shifting phenological transition dates. We also performed a sensitivity analysis of the full-memory-effect LSTM model to assess its plausibility, revealing its coherence with established knowledge of vegetation phenology sensitivity to meteorological conditions, particularly changes in temperature. Our study highlights that (1) multi-variate meteorological memory effects play a crucial role in vegetation phenology, and (2) deep learning opens up new avenues for improving the representation of vegetation phenological processes in land surface models via a hybrid modelling approach.

Geology↗
DOE OSTI2014

An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems

Emerging applications such as data mining, bioinformatics, knowledge discovery, social network analysis are irregular. They use data structures based on pointers or linked lists, such as graphs, unbalanced trees or unstructures grids, which generates unpredictable memory accesses. These data structures usually are large, but difficult to partition. These applications mostly are memory bandwidth bounded and have high synchronization intensity. However, they also have large amounts of inherent dynamic parallelism, because they potentially perform a task for each one of the element they are exploring. Several efforts are looking at accelerating these applications on hybrid architectures, which integrate general purpose processors with reconfigurable devices. Some solutions, which demonstrated significant speedups, include custom-hand tuned accelerators or even full processor architectures on the reconfigurable logic. In this paper we present an approach for the automatic synthesis of accelerators from C, targeted at irregular applications. In contrast to typical High Level Synthesis paradigms, which construct a centralized Finite State Machine, our approach generates dynamically scheduled hardware components. While parallelism exploitation in typical HLS-generated accelerators is usually bound within a single execution flow, our solution allows concurrently running multiple execution flow, thus also exploiting the coarser grain task parallelism of irregular applications. Our approach supports multiple, multi-ported and distributed memories, and atomic memory operations. Its main objective is parallelizing as many memory operations as possible, independently from their execution time, to maximize the memory bandwidth utilization. This significantly differs from current HLS flows, which usually consider a single memory port and require precise scheduling of memory operations. A key innovation of our approach is the generation of a memory interface controller, which dynamically maps concurrent memory accesses to multiple ports. We present a case study on a typical irregular kernel, Graph Breadth First search (BFS), exploring different tradeoffs in terms of parallelism and number of memories.

BFS↗
DOE OSTI2015

Atomic memory access hardware implementations

Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Understanding the Impact of Memory Access Patterns in Intel Processors

Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.

Alaul haque monil, Mohammad↗
DOE OSTI2015

Effects of non-invasive brain stimulation on associative memory

Associative memory refers to remembering the association between two items, such as a face and a name. It is a crucial part of daily life, but it is also one of the first aspects of memory performance that is impacted by aging and by Alzheimer’s disease. Evidence suggests that transcranial direct current stimulation (tDCS) can improve memory performance, but few tDCS studies have investigated its impact on associative memory. In addition, no prior study of the effects of tDCS on memory performance has systematically evaluated the impact of tDCS on different types of memory assessments, such as recognition and recall tests. In this study, we measured the effects of tDCS on associative memory performance in healthy adults, using both recognition and recall tests. Participants studied face-name pairs while receiving either active (30 minutes, 2 mA) or sham (30 minutes, 0.1 mA) stimulation with the anode placed at F9 and the cathode placed on the contralateral upper arm. Participants in the active stimulation group performed significantly better on the recall test than participants in the sham group, recalling 50% more names, on average, and making fewer recall errors. However, the two groups did not differ significantly in terms of their performance on the recognition memory test. This investigation provides evidence that stimulation at the time of study improves associative memory encoding, but that this memory benefit is evident only under certain retrieval conditions.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2022

A Double-Edged Sword: The Role of Prior Knowledge in Memory Aging

People accumulate knowledge throughout their lifespan and the accumulated knowledge influences how we encode and retrieve information in memory processing. This study aims to investigate the role of knowledge in associative memory across the adult lifespan, and specifically examines the effects of two material properties that interact with prior knowledge: congruency – whether the material is congruent with people’s prior knowledge, and ambiguity – whether the material is ambiguous to interpret based on prior knowledge. 273 participants (aged 22–70 years old) completed an incidental memory task online. Participants were shown pictures depicting an object in a scene and judged if the object was likely or unlikely to be in the particular scene. Later, in the recognition test, participants were asked to identify if the exact picture was presented earlier. The pictures were manipulated to have varying levels of congruency, meaning that some depicted likely object–scene pairs and some unlikely. We also measured how different the likely/unlikely judgment for each object–scene pair was across all participants to determine the ambiguity level of the object–scene pair: some were more likely to receive diverse responses across people, whereas others are unambiguously consistent (or inconsistent) with common knowledge shared by most people. We used mixed-effects logistic regressions to predict memory outcome for each trial as a function of age, age 2 , congruency/ambiguity, and their interactions. The object–scene pairs perceived as congruent had higher hit rates than incongruent ones, as well as higher false alarm rates, especially in middle-aged and older people. Higher ambiguity was also related to both greater true and false memory, independent of age. Finally, the effect of ambiguity only emerged when the object–scene pair was perceived incongruent. The results suggest that people rely on prior knowledge to process new information and that this reliance improves hit responses, but also induces false memories particularly for middle-aged and older people, suggesting a double-edged role of knowledge in associative memory and its disproportionate influence on memory aging. Over-reliance on knowledge in older adults, which has been suspected in other cognitive processes, may be one of the mechanisms underlying associative memory decrease in aging.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2021

Non-Markovian dynamics of open quantum system with memory

Highlights: • Non-Markovian master equation for open quantum system with power-law memory is proposed. • Non-Markovian dynamics of two-level quantum system with memory is described. • Solutions of non-Markovian quantum master equations are derived. • Complete positivity and bi-positivity in non-Markovian quantum dynamics with memory are described. • Exact solution of non-Markovian equations of system with memory is proposed. In this paper, non-Markovian generalization of master equation for open quantum system is proposed. Non-Markovian dynamics of two-level quantum system with memory and interaction with environment is described. To describe this system, the Gorini–Kossakowski–Sudarshan equation for open quantum states is generalized by taking into account power-law fading memory. The non-Markovian quantum processes with power-law memory are described by using integration and differentiation of non-integer orders. Complete positivity and bi-positivity in non-Markovian quantum dynamics with memory are described. An example of two-level quantum systems with power-law memory is suggested. Exact solution of the non-Markovian master equations of two-level open quantum systems with memory is derived.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2017

Bisphenol A impairs the memory function and glutamatergic homeostasis in a sex-dependent manner in mice: Beneficial effects of diphenyl diselenide

Bisphenol A (BPA) is a compound integrated in commodities, which consequently increases the human exposure to this toxicant. The deleterious effects of BPA exposure during periods of brain development have been documented mainly concerning the impairment in memory functions. Diphenyl diselenide (PhSe){sub 2}, an organoselenium compound, shows protective/restorative effects against memory deficits in experimental models. Thus, this study investigated the effects of (PhSe){sub 2} on the memory impairments induced by BPA exposure to male and female mice and the possible involvement of glutamatergic system in these effects. Three-week-old male and female Swiss mice received BPA (5 mg/kg), intragastrically, from 21st to 60th postnatal day. After, the animals were intragastrically treated with (PhSe){sub 2} (1 mg/kg) during seven days. The mice performed the behavioral memory tests and the [{sup 3}H] glutamate uptake and NMDA receptor subunits (2A and 2B) analyses were carried out in the hippocampus and cerebral cortex of mice. The results demonstrated that the BPA exposure induced impairment of object recognition memory in both sexes. However, it caused impairments in spatial memory in female and in the passive avoidance memory in male mice. Besides, BPA caused a decrease in the [{sup 3}H] glutamate uptake and NMDA receptor subunit levels in the cortical and hippocampal regions depending on the sex. Treatment with (PhSe){sub 2} reversed in a sex-independent manner the behavioral impairments and molecular alterations. In conclusion, BPA had a negative effect in different memory types as well as in the glutamatergic parameters in a sex-dependent manner and (PhSe){sub 2} treatment was effective against these alterations. - Highlights: • BPA exposure induced memory impairment in a sex dependent manner in mice. • (PhSe){sub 2} reversed memory impairments caused by BPA exposure in mice. • (PhSe){sub 2} modulated hippocampal and cortical [{sup 3}H]glutamate uptake in mice. • (PhSe){sub 2} restored the hippocampal and cortical NMDA receptor subunits levels.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2021

Performance of CUDA Unified Memory in CMS Heterogeneous Pixel Reconstruction

The management of separate memory spaces of CPUs and GPUs brings an additional burden to the development of software for GPUs. To help with this, CUDA unified memory provides a single address space that can be accessed from both CPU and GPU. The automatic data transfer mechanism is based on page faults generated by the memory accesses. This mechanism has a performance cost, that can be with explicit memory prefetch requests. Various hints on the inteded usage of the memory regions can also be given to further improve the performance. The overall effect of unified memory compared to an explicit memory management can depend heavily on the application. In this paper we evaluate the performance impact of CUDA unified memory using the heterogeneous pixel reconstruction code from the CMS experiment as a realistic use case of a GPU-targeting HEP reconstruction software. We also compare the programming model using CUDA unified memory to the explicit management of separate CPU and GPU memory spaces.

Kortelainen, Matti J.↗
DOE OSTI2019

Thread Batching for High-performance Energy-efficient GPU Memory Design

Massive multi-threading in GPU imposes tremendous pressure on memory subsystems. Due to rapid growth in thread-level parallelism of GPU and slowly improved peak memory bandwidth, memory becomes a bottleneck of GPU’s performance and energy efficiency. In this article, we propose an integrated architectural scheme to optimize the memory accesses and therefore boost the performance and energy efficiency of GPU. First, we propose a thread batch enabled memory partitioning (TEMP) to improve GPU memory access parallelism. In particular, TEMP groups multiple thread blocks that share the same set of pages into a thread batch and applies a page coloring mechanism to bound each stream multiprocessor (SM) to the dedicated memory banks. After that, TEMP dispatches the thread batch to an SM to ensure high-parallel memory-access streaming from the different thread blocks. Second, a thread batch-aware scheduling (TBAS) scheme is introduced to improve the GPU memory access locality and to reduce the contention on memory controllers and interconnection networks. Experimental results show that the integration of TEMP and TBAS can achieve up to 10.3% performance improvement and 11.3% DRAM energy reduction across diverse GPU applications. We also evaluate the performance interference of the mixed CPU+GPU workloads when they are run on a heterogeneous system that employs our proposed schemes. Our results show that a simple solution can effectively ensure the efficient execution of both GPU and CPU applications.

Computer Science↗
DOE OSTI2019

Evaluating the effectiveness of program data features for guiding memory management

Recent trends have led to the adoption of larger and more complex memory systems, often with multiple tiers of memory performance within the same platform. To utilize complex memory systems efficiently, current data management strategies must be altered to map usage demands to the underlying hardware. Applications, as the generators of memory accesses, are well-suited to guide this process, but building and maintaining separate source code versions for different memory systems is not feasible in most cases. One potential solution is to employ automated program profiling and analysis to facilitate the production of application-based guidance. By attaching memory usage information to static or lightweight program features, compilers and runtime systems can generate fine-grained guidance without additional efforts from users or developers. Recent works have employed this approach with some success, but it is not clear which program features are most useful for guiding data management.This work evaluates the effectiveness of using different program data features to predict memory usage and guide memory management. It employs a custom set of simulation tools, based in the Intel® Pin framework, to collect and analyze the usage characteristics of application data associated with common program data features, such as allocation sites, types, and context. The results show that even relatively simple features, such as object size, are useful for selecting data with similar usage properties, but finer-grained features, such as the instructions that access a particular object, are often much more effective. Additionally, this work evaluates the performance of using different data features and different program inputs to guide data placement on a heterogeneous memory platform with a limited amount of high performance memory.

Effler, T. Chad↗